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authorNick Vaccaro <nvaccaro@chromium.org>2018-01-21 22:14:40 -0800
committerMartin Roth <martinroth@google.com>2018-01-30 23:14:45 +0000
commitaf0e7d18a7f21a7a92b890eaffab2b968542881e (patch)
tree1c865a35189886e1593c69904de60a7d0c5fe327 /src/mainboard/google/zoombini
parent6978971c4a36f5dd0ba3f302236e94a9559fb7bb (diff)
downloadcoreboot-af0e7d18a7f21a7a92b890eaffab2b968542881e.tar.xz
mainboard/google/zoombini/variants/meowth: Fix USB OC settings
Set USB2 port 0 & 1 to use OC2 and OC3 respectively. Previous settings were causing false overcurrent conditions as OC0 and OC1 were used for other purposes. Remove initialization of unused usb3 ports, and configure the ports we use (usb3 ports 0 & 1) to use OC2 and OC3, respectively. BUG=b:72250084 BRANCH=none TEST=Verify meowth can recognize and boot off a kernel on USB drive. Change-Id: I528b67d80a1da84e5307facb40de545089979f57 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zoombini')
-rw-r--r--src/mainboard/google/zoombini/variants/meowth/devicetree.cb14
1 files changed, 5 insertions, 9 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index aed4a19527..01fe0c5a80 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -39,9 +39,9 @@ chip soc/intel/cannonlake
.early_init = 1,
}"
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC3)"
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)"
@@ -50,12 +50,8 @@ chip soc/intel/cannonlake
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)"
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"
device domain 0 on
device pci 00.0 on end # Host Bridge