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| author | Raul E Rangel <rrangel@chromium.org> | 2020-05-20 14:07:41 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2020-05-27 23:18:12 +0000 |
| commit | b3c41329fdca84a251c183bbc2b0767978e9d96f (patch) | |
| tree | 47003eae89ad4f6dd86edb52b1fe203d7e7b14b5 /src/mainboard/google/zork/dsdt.asl | |
| parent | fc9b8b916f7bc0c6ac1579b915937ed23ea3327a (diff) | |
| download | coreboot-b3c41329fdca84a251c183bbc2b0767978e9d96f.tar.xz | |
mb/google/zork: Add Picasso based Zork mainboard and variants
This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/zork/dsdt.asl | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl new file mode 100644 index 0000000000..0831ddd5b7 --- /dev/null +++ b/src/mainboard/google/zork/dsdt.asl @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <variant/ec.h> + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> + +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include <variant/acpi/mainboard.asl> + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include <variant/acpi/sleep.asl> + + /* Contains _SWS methods */ + #include <acpi_wake_source.asl> + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe the SOC */ + #include <soc.asl> + + } /* End \_SB scope */ + + /* Thermal handler */ + #include <variant/acpi/thermal.asl> + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + /* ACPI code for EC I2C Audio Tunnel */ + #include <variant/acpi/audio.asl> + } +} +/* End of ASL file */ |