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authorRaul E Rangel <rrangel@chromium.org>2020-05-20 14:07:41 -0600
committerMartin Roth <martinroth@google.com>2020-05-27 23:18:12 +0000
commitb3c41329fdca84a251c183bbc2b0767978e9d96f (patch)
tree47003eae89ad4f6dd86edb52b1fe203d7e7b14b5 /src/mainboard/google/zork/ec.c
parentfc9b8b916f7bc0c6ac1579b915937ed23ea3327a (diff)
downloadcoreboot-b3c41329fdca84a251c183bbc2b0767978e9d96f.tar.xz
mb/google/zork: Add Picasso based Zork mainboard and variants
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/ec.c')
-rw-r--r--src/mainboard/google/zork/ec.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/ec.c b/src/mainboard/google/zork/ec.c
new file mode 100644
index 0000000000..4c4329dd07
--- /dev/null
+++ b/src/mainboard/google/zork/ec.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <soc/southbridge.h>
+#include <variant/ec.h>
+
+static void ramstage_ec_init(void)
+{
+ const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ };
+
+ printk(BIOS_DEBUG, "mainboard: EC init\n");
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
+
+void mainboard_ec_init(void)
+{
+ if (ENV_RAMSTAGE)
+ ramstage_ec_init();
+}