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authorFurquan Shaikh <furquan@google.com>2020-07-15 13:58:59 -0700
committerAaron Durbin <adurbin@chromium.org>2020-07-16 16:45:27 +0000
commit56f949cd0c793e0a43d4339ce6e2e8003f5ce978 (patch)
tree12c80f29d1c4940ce51d52ee8df5f9e2e5af78d5 /src/mainboard/google/zork/romstage.c
parent6a5c77cc846384dbc10c3546f70245025787ef08 (diff)
downloadcoreboot-56f949cd0c793e0a43d4339ce6e2e8003f5ce978.tar.xz
mb/google/zork: Drop variant_romstage_gpio_table()
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in romstage. This change moves the configuration of PCIe related GPIOs to variant_pcie_gpio_configure() to keep all the configuration for WiFi and non-WiFi PCIe pads in one place. It also drops the function variant_romstage_gpio_table() as it is unused. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/romstage.c')
-rw-r--r--src/mainboard/google/zork/romstage.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c
index bd4c96eebe..39f23cff83 100644
--- a/src/mainboard/google/zork/romstage.c
+++ b/src/mainboard/google/zork/romstage.c
@@ -7,10 +7,5 @@
void mainboard_romstage_entry_s3(int s3_resume)
{
- size_t num_gpios;
- const struct soc_amd_gpio *gpios;
-
- gpios = variant_romstage_gpio_table(&num_gpios);
- program_gpios(gpios, num_gpios);
- variant_pcie_power_reset_configure();
+ variant_pcie_gpio_configure();
}