diff options
author | Rob Barnes <robbarnes@google.com> | 2020-07-13 20:15:39 -0600 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-16 00:16:40 +0000 |
commit | 9754f38e8242580bc338aa510bbebd63e544f7b1 (patch) | |
tree | 52b7627ba481fa99662f703fe151dec9b55c43cc /src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb | |
parent | 31b7d95350728431ebd9991a45a72be6425ebeb7 (diff) | |
download | coreboot-9754f38e8242580bc338aa510bbebd63e544f7b1.tar.xz |
mb/google/zork: Remove redundant PCI info from overridetrees
This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb
domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.
BUG=b:157580724
TEST=Boot zork, usb functional
Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb')
-rw-r--r-- | src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ec7a706802..585f5a7183 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -201,6 +201,8 @@ chip soc/amd/picasso device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME device pci 8.0 on end # Dummy Host Bridge, must be enabled device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 0.0 on end # Internal GPU @@ -340,6 +342,7 @@ chip soc/amd/picasso end end end + device pci 14.6 off end # Non-Functional SDHCI device pci 18.0 on end # Data fabric [0-7] device pci 18.1 on end device pci 18.2 on end |