diff options
author | Raul E Rangel <rrangel@chromium.org> | 2020-05-20 14:07:41 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2020-05-27 23:18:12 +0000 |
commit | b3c41329fdca84a251c183bbc2b0767978e9d96f (patch) | |
tree | 47003eae89ad4f6dd86edb52b1fe203d7e7b14b5 /src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | |
parent | fc9b8b916f7bc0c6ac1579b915937ed23ea3327a (diff) | |
download | coreboot-b3c41329fdca84a251c183bbc2b0767978e9d96f.tar.xz |
mb/google/zork: Add Picasso based Zork mainboard and variants
This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c')
-rw-r--r-- | src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | 187 |
1 files changed, 187 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c new file mode 100644 index 0000000000..fb96ff2537 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/bsd/compiler.h> +#include <soc/soc_util.h> + +void __weak variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs, + size_t *pcie_num, + const picasso_fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *pcie_descs = baseboard_get_pcie_descriptors(pcie_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +/* FP5 package can support Type 1 (Picasso) and Type 2 (Dali), however some + * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. + * Those parts need to be configured as Type 2. */ + +static const picasso_fsp_pcie_descriptor pco_pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 3, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +static const picasso_fsp_pcie_descriptor dali_pcie_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = NVME_START_LANE, + .end_lane = NVME_END_LANE, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = NVME_CLKREQ, + .clk_pm_support = true, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = WLAN_START_LANE, + .end_lane = WLAN_END_LANE, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = WLAN_CLKREQ, + .clk_pm_support = true, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = SD_START_LANE, + .end_lane = SD_END_LANE, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = SD_CLKREQ, + } +}; + +const picasso_fsp_pcie_descriptor *baseboard_get_pcie_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_dali()) { + *num = ARRAY_SIZE(dali_pcie_descriptors); + return dali_pcie_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_pcie_descriptors); + return pco_pcie_descriptors; + } + +} + +static const picasso_fsp_ddi_descriptor pco_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT1 HDMI + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP2, DB OPT1 USB-C1 + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { + // DDI3, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const picasso_fsp_ddi_descriptor dali_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +const picasso_fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_dali()) { + *num = ARRAY_SIZE(dali_ddi_descriptors); + return dali_ddi_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_ddi_descriptors); + return pco_ddi_descriptors; + } +} |