mb/google/zork: Add Picasso based Zork mainboard and variants

This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.

See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork

Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
  set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
  binaries since they haven't been published. To get a working build
  a custom config that sets FSP_X_FILE is required.

BUG=b:157140753
TEST=Build trembyle and boot to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

13 files changed, 422 insertions, 0 deletions

diff --git a/src/mainboard/google/zork/variants/dalboz/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/Makefile.inc
new file mode 100644
index 0000000000..a616e2fdc0
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/Makefile.inc
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+subdirs-y += ./spd
+
+romstage-y += romstage.c
+
+ramstage-y += gpio.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/zork/variants/dalboz/gpio.c b/src/mainboard/google/zork/variants/dalboz/gpio.c
new file mode 100644
index 0000000000..3e705a6b34
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/gpio.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <ec/google/chromeec/ec.h>
+
+/* This table is used by dalboz variant with board version < 2. */
+static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
+	/* USB_OC2_L - USB A0 & A1 */
+	PAD_NF(GPIO_18, USB_OC2_L, PULL_UP),
+	/* Unused */
+	PAD_GPI(GPIO_143, PULL_DOWN),
+};
+
+const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
+{
+	uint32_t board_version;
+
+	/*
+	 * If board version cannot be read, assume that this is an older revision of the board
+	 * and so apply overrides. If board version is provided by the EC, then apply overrides
+	 * if version < 2.
+	 */
+	if (google_chromeec_cbi_get_board_version(&board_version))
+		board_version = 1;
+
+	if (board_version < 2) {
+		*size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
+		return bid_1_gpio_set_stage_ram;
+	}
+
+	*size = 0;
+	return NULL;
+}
diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl
new file mode 100644
index 0000000000..900e36f277
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/audio.asl>
diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..a1161edb5f
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/mainboard.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/mainboard.asl>
diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl
new file mode 100644
index 0000000000..8177a9df2a
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/sleep.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/sleep.asl>
diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl
new file mode 100644
index 0000000000..7a793d8102
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/thermal.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/thermal.asl>
diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h b/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h
new file mode 100644
index 0000000000..9e61a440cf
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/include/variant/ec.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/ec.h>
diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h
new file mode 100644
index 0000000000..dfaeec3ae1
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/include/variant/gpio.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h
new file mode 100644
index 0000000000..2af647973d
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/include/variant/thermal.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/thermal.h>
diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb
new file mode 100644
index 0000000000..8ac3348e2a
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+chip soc/amd/picasso
+
+	# Start : OPN Performance Configuration
+	# See devhub #56670 Chapter 5 for documentation
+	# For the below fields, 0 indicates use SOC default
+
+	# System config index
+	register "system_config" = "1"
+
+	# Set STAPM confiuration. All of these fields must be set >0 to take affect
+	register "slow_ppt_limit" = "6000" #mw
+	register "fast_ppt_limit" = "9000" #mw
+	register "slow_ppt_time_constant" = "5" #second
+	register "stapm_time_constant" = "2500" #second
+	register "sustained_power_limit" = "4800" #mw
+
+	# End : OPN Performance Configuration
+
+	# I2C2 for touchscreen and trackpad
+	register "i2c[2]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 18,  /* 0 to 2.31 (3.3 * .7) */
+		.fall_time_ns = 57,  /* 2.31 to 0 */
+	}"
+
+	# I2C3 for H1
+	register "i2c[3]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 184, /* 0 to 1.26v (1.8 * .7) */
+		.fall_time_ns = 42,  /* 1.26v to 0 */
+		.early_init = true,
+	}"
+
+	# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
+	device domain 0 on
+		subsystemid 0x1022 0x1510 inherit
+		device pci 8.1 on      # Internal GPP Bridge 0 to Bus A
+			device pci 0.3 on  end # USB 3.1
+		end
+	end # domain
+
+	device mmio 0xfedc4000 on # APU_I2C2_BASE
+		chip drivers/i2c/generic
+			register "hid" = ""RAYD0001""
+			register "desc" = ""Raydium Touchscreen""
+			register "probed" = "1"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "reset_delay_ms" = "20"
+			register "has_power_resource" = "1"
+			device i2c 39 on end
+		end
+		chip drivers/i2c/generic
+			register "hid" = ""ELAN0001""
+			register "desc" = ""ELAN Touchscreen""
+			register "probed" = "1"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "reset_delay_ms" = "20"
+			register "has_power_resource" = "1"
+			device i2c 10 on end
+		end
+		chip drivers/i2c/hid
+			register "generic.hid" = ""SYTS7817""
+			register "generic.desc" = ""Synaptics Touchscreen""
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "generic.probed" = "1"
+			register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "generic.reset_delay_ms" = "45"
+			register "generic.has_power_resource" = "1"
+			register "generic.disable_gpio_export_in_crs" = "1"
+			register "hid_desc_reg_offset" = "0x20"
+			device i2c 20 on end
+		end
+		chip drivers/i2c/hid
+			register "generic.hid" = ""GDIX0000""
+			register "generic.desc" = ""Goodix Touchscreen""
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+			register "generic.probed" = "1"
+			register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+			register "generic.reset_delay_ms" = "120"
+			register "generic.has_power_resource" = "1"
+			register "hid_desc_reg_offset" = "0x01"
+			device i2c 5d on end
+		end
+		chip drivers/i2c/generic
+			register "hid" = ""ELAN0000""
+			register "desc" = ""ELAN Touchpad""
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+			register "wake" = "7"
+			register "probed" = "1"
+			device i2c 15 on end
+		end
+		chip drivers/i2c/hid
+			register "generic.hid" = ""PNP0C50""
+			register "generic.desc" = ""Synaptics Touchpad""
+			register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+			register "generic.wake" = "7"
+			register "generic.probed" = "1"
+			register "hid_desc_reg_offset" = "0x20"
+			device i2c 2c on end
+		end
+	end
+end	# chip soc/amd/picasso
diff --git a/src/mainboard/google/zork/variants/dalboz/romstage.c b/src/mainboard/google/zork/variants/dalboz/romstage.c
new file mode 100644
index 0000000000..42e36c4525
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/romstage.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <stddef.h>
+#include <soc/romstage.h>
+#include <baseboard/variants.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+void variant_romstage_entry(void)
+{
+	uint32_t board_version;
+
+	if (google_chromeec_cbi_get_board_version(&board_version))
+		board_version = 1;
+
+	if (board_version < 2) {
+		/* SET PCIE_RST0_L HIGH */
+		gpio_set(WIFI_PCIE_RESET_L, 1);
+	} else {
+		/* SET PCIE_RST1_L HIGH */
+		gpio_set(PCIE_RST1_L, 1);
+	}
+}
diff --git a/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc
new file mode 100644
index 0000000000..7baf8be205
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/spd/Makefile.inc
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Ordered List of APCB entries, up to 16.
+# Entries should match this pattern {NAME}_x{1,2}
+# There should be a matching SPD hex file in SPD_SOURCES_DIR
+# matching the pattern {NAME}.spd.hex
+# The _x{1,2} suffix denotes single or dual channel
+# Alternatively, generated APCBs stored at
+# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
+APCB_SOURCES =  hynix-HMA851S6CJR6N-VK_x1	# 0b0000
+APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1	# 0b0001
+APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1	# 0b0010
+APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1	# 0b0011
+APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1	# 0b0100
+APCB_SOURCES += empty				# 0b0101
+APCB_SOURCES += empty				# 0b0110
+APCB_SOURCES += empty				# 0b0111
+APCB_SOURCES += empty				# 0b1000
+APCB_SOURCES += empty				# 0b1001
+APCB_SOURCES += empty				# 0b1010
+APCB_SOURCES += empty				# 0b1011
+APCB_SOURCES += empty				# 0b1100
+APCB_SOURCES += empty				# 0b1101
+APCB_SOURCES += empty				# 0b1110
+APCB_SOURCES += empty				# 0b1111
diff --git a/src/mainboard/google/zork/variants/dalboz/variant.c b/src/mainboard/google/zork/variants/dalboz/variant.c
new file mode 100644
index 0000000000..aae8f03058
--- /dev/null
+++ b/src/mainboard/google/zork/variants/dalboz/variant.c
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <drivers/i2c/generic/chip.h>
+#include <soc/pci_devs.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/i2c_tunnel/chip.h>
+#include <string.h>
+
+#define EC_PNP_ID 0x0c09
+
+/* Look for an EC device of type PNP with id 0x0c09 */
+static bool match_ec_dev(DEVTREE_CONST struct device *dev)
+{
+	if (dev->path.type != DEVICE_PATH_PNP)
+		return false;
+
+	if (dev->path.pnp.port != EC_PNP_ID)
+		return false;
+
+	return true;
+}
+
+extern struct chip_operations drivers_i2c_generic_ops;
+
+/* Look for an I2C device with HID "10EC5682" */
+static bool match_audio_dev(DEVTREE_CONST struct device *dev)
+{
+	struct drivers_i2c_generic_config *cfg;
+
+	if (dev->chip_ops != &drivers_i2c_generic_ops)
+		return false;
+
+	cfg = dev->chip_info;
+
+	return !strcmp(cfg->hid, "10EC5682");
+}
+
+extern struct chip_operations ec_google_chromeec_i2c_tunnel_ops;
+
+/* Look for Cros EC tunnel device which has audio device under it. */
+static bool match_audio_tunnel(DEVTREE_CONST struct device *dev)
+{
+	const struct device *audio_dev;
+
+	if (dev->chip_ops != &ec_google_chromeec_i2c_tunnel_ops)
+		return false;
+
+	audio_dev = dev_find_matching_device_on_bus(dev->link_list, match_audio_dev);
+
+	if (!audio_dev)
+		return false;
+
+	return true;
+}
+
+/*
+ * This is to allow support for audio on older board versions (< 2). [b/153458561]. This
+ * should be removed once these boards are phased out.
+ */
+static void update_audio_configuration(void)
+{
+	uint32_t board_version;
+	const struct device *lpc_controller;
+	const struct device *ec_dev;
+	const struct device *i2c_tunnel_dev;
+	struct ec_google_chromeec_i2c_tunnel_config *cfg;
+
+	/* If CBI board version cannot be read, assume this is an older revision of hardware. */
+	if (google_chromeec_cbi_get_board_version(&board_version) != 0)
+		board_version = 1;
+
+	if (board_version >= 2)
+		return;
+
+	lpc_controller = SOC_LPC_DEV;
+	if (lpc_controller == NULL) {
+		printk(BIOS_ERR, "%s: LPC controller device not found!\n", __func__);
+		return;
+	}
+
+	ec_dev = dev_find_matching_device_on_bus(lpc_controller->link_list, match_ec_dev);
+
+	if (ec_dev == NULL) {
+		printk(BIOS_ERR, "%s: EC device not found!\n", __func__);
+		return;
+	}
+
+	i2c_tunnel_dev = dev_find_matching_device_on_bus(ec_dev->link_list, match_audio_tunnel);
+
+	if (i2c_tunnel_dev == NULL) {
+		printk(BIOS_ERR, "%s: I2C tunnel device not found!\n", __func__);
+		return;
+	}
+
+	cfg = i2c_tunnel_dev->chip_info;
+	if (cfg == NULL) {
+		printk(BIOS_ERR, "%s: I2C tunnel device config not found!\n", __func__);
+		return;
+	}
+
+	cfg->remote_bus = 5;
+}
+
+static int sku_has_emmc(void)
+{
+	uint32_t board_sku = sku_id();
+
+	/* Factory flow requires all OS boot media to be enabled. */
+	if (boot_is_factory_unprovisioned())
+		return 1;
+
+	/* FIXME: This needs to be fw_config controlled. */
+	/* Enable emmc0 for unknown skus. Only sku3/0xC really has it. */
+	if (board_sku == 0x5A80000C || board_sku == 0x5A800003 || board_sku == CROS_SKU_UNKNOWN)
+		return 1;
+
+	return 0;
+}
+
+void variant_devtree_update(void)
+{
+	struct soc_amd_picasso_config *cfg;
+
+	cfg = config_of_soc();
+
+	if (sku_has_emmc()) {
+		if (sku_id() == 0x5A800003)
+			/* rev0 boards have issues with HS400 */
+			cfg->sd_emmc_config = SD_EMMC_EMMC_HS200;
+	} else {
+		cfg->sd_emmc_config = SD_EMMC_DISABLE;
+	}
+
+	update_audio_configuration();
+}
+
+/* FIXME: Comments seem to suggest these are not entirely correct. */
+static const picasso_fsp_ddi_descriptor non_hdmi_ddi_descriptors[] = {
+	{
+		// DDI0, DP0, eDP
+		.connector_type = EDP,
+		.aux_index = AUX1,
+		.hdp_index = HDP1
+	},
+	{
+		// DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub
+		.connector_type = DP,
+		.aux_index = AUX2,
+		.hdp_index = HDP2
+	},
+	{
+		// DP2 pins not connected on Dali
+		// DDI2, DP3, USB-C0
+		.connector_type = DP,
+		.aux_index = AUX4,
+		.hdp_index = HDP4,
+	}
+};
+
+static const picasso_fsp_ddi_descriptor hdmi_ddi_descriptors[] = {
+	{ // DDI0, DP0, eDP
+		.connector_type = EDP,
+		.aux_index = AUX1,
+		.hdp_index = HDP1
+	},
+	{ // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub
+		.connector_type = HDMI,
+		.aux_index = AUX2,
+		.hdp_index = HDP2
+	},
+	// DP2 pins not connected on Dali
+	{ // DDI2, DP3, USB-C0
+		.connector_type = DP,
+		.aux_index = AUX4,
+		.hdp_index = HDP4,
+	}
+};
+
+void variant_get_pcie_ddi_descriptors(const picasso_fsp_pcie_descriptor **pcie_descs,
+				      size_t *pcie_num,
+				      const picasso_fsp_ddi_descriptor **ddi_descs,
+				      size_t *ddi_num)
+{
+	uint32_t board_sku = sku_id();
+
+	*pcie_descs = baseboard_get_pcie_descriptors(pcie_num);
+
+	/* SKU 1, A, and D DB have HDMI, as well as unknown */
+	/* FIXME: this needs to be fw_config controlled. */
+	if ((board_sku == 0x5A80000A) || (board_sku == 0x5A80000D) || (board_sku == 0x5A800001)
+	    || (board_sku == CROS_SKU_UNKNOWN)) {
+		*ddi_descs = &hdmi_ddi_descriptors[0];
+		*ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors);
+	} else {
+		*ddi_descs = &non_hdmi_ddi_descriptors[0];
+		*ddi_num = ARRAY_SIZE(non_hdmi_ddi_descriptors);
+	}
+}