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authorNick Vaccaro <nvaccaro@google.com>2018-06-06 17:05:15 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-06-11 08:32:06 +0000
commit0a2e39d2608f8ca99d3df58e9c27475fa38bee95 (patch)
treeef7e5568a6058bc5b8aafcda8b801686bfed6c09 /src/mainboard/google
parentabe73975f0090a169d381a61923e17cbd6502c93 (diff)
downloadcoreboot-0a2e39d2608f8ca99d3df58e9c27475fa38bee95.tar.xz
mb/google/poppy/variants/nocturne: enable nvme
- configure GPP_B7 (PCIE_NVME_CLKREQ_ODL) for NF1 - enable root port 9 - add nvme register settings to devicetree BUG=b:78122599 BRANCH=chromeos-2016.05 TEST='emerge-nocturne depthcharge coreboot chromeos-bootimage', boot to kernel, and verify /dev/nvme* entries exist. CQ-DEPEND=CL:1090070 Change-Id: I0070d33b1ed09bd1f51a680d92ddb7e2bcb1ebc2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/26933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb16
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/gpio.c4
2 files changed, 17 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 5b4c924296..f746c080bf 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -160,6 +160,20 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
+ # Root port 9 (x2)
+ # PcieRpEnable: Enable root port
+ # PcieRpClkReqSupport: Enable CLKREQ#
+ # PcieRpClkReqNumber: Uses SRCCLKREQ2#
+ # PcieRpClkSrcNumber: Uses 2
+ # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+ # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "2"
+ register "PcieRpClkSrcNumber[8]" = "2"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+
# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
@@ -326,7 +340,7 @@ chip soc/intel/skylake
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index be76b64267..ad7f963fe9 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -77,8 +77,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_B5),
/* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
PAD_CFG_GPI_GPIO_DRIVER(GPP_B6, NONE, DEEP),
- /* B7 : SRCCLKREQ2# ==> NC */
- PAD_CFG_NC(GPP_B7),
+ /* B7 : SRCCLKREQ2# ==> PCIE_NVME_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
PAD_CFG_GPO(GPP_B8, 0, RSMRST),
/* B9 : SRCCLKREQ4# ==> NC */