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| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 17:20:16 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-14 11:05:51 +0000 |
| commit | 233ae1919b72434ca6cd783c9a946d32953bc7e9 (patch) | |
| tree | 52034859f35a1ab58e6f870b2b040e33d8eeda5d /src/mainboard/google | |
| parent | 68cf57cf33141edcc8b4b1250b099884e0553457 (diff) | |
| download | coreboot-233ae1919b72434ca6cd783c9a946d32953bc7e9.tar.xz | |
soc/intel/braswell: Clean up devicetree settings
Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.
Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/cyan/devicetree.cb | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 91e9795f9b..cec1682ed1 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -7,14 +7,9 @@ chip soc/intel/braswell # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "1" register "PcdCaMirrorEn" = "1" @@ -40,9 +35,6 @@ chip soc/intel/braswell register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -68,9 +60,7 @@ chip soc/intel/braswell register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "1" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" |