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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-05-18 17:46:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-05-20 09:12:28 +0000
commit38c308515c4a983f361d287a3cbeec3ee36c52ae (patch)
tree80d93170f29c3d1597f4506b6a7f7119e08ef382 /src/mainboard/google
parent88712991ba390c309b4586864aa04a9680fd8320 (diff)
downloadcoreboot-38c308515c4a983f361d287a3cbeec3ee36c52ae.tar.xz
mb/google/deltaur: Add tcss.asl
Add tcss.asl to support TCSS power management. For the detail please refer cb:39785. BUG=none TEST=Check TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3 /sys/bus/pci/devices/bus:device:func/power suspend and active time can increase. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I432f3d6643de13b08c07e47f799c0ecdfe047de6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41506 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/deltaur/dsdt.asl1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl
index fe86e15b45..fac58bdf42 100644
--- a/src/mainboard/google/deltaur/dsdt.asl
+++ b/src/mainboard/google/deltaur/dsdt.asl
@@ -25,6 +25,7 @@ DefinitionBlock(
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
+ #include <soc/intel/tigerlake/acpi/tcss.asl>
}
}