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authorPatrick Georgi <pgeorgi@chromium.org>2015-06-22 19:43:18 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-06-30 21:47:22 +0200
commit4d6ad838e77ad37749f11a4013a1d879e6286fee (patch)
tree475cfdfd1652a13deabb611d337fdf79fcd43605 /src/mainboard/google
parentfd49d6faf98eb45006a20869da798558cea9606e (diff)
downloadcoreboot-4d6ad838e77ad37749f11a4013a1d879e6286fee.tar.xz
google/smaug: add new mainboard
This is an nvidia t210 based board. This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10635 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/smaug/Kconfig109
-rw-r--r--src/mainboard/google/smaug/Kconfig.name2
-rw-r--r--src/mainboard/google/smaug/Makefile.inc52
-rw-r--r--src/mainboard/google/smaug/bct/Makefile.inc30
-rw-r--r--src/mainboard/google/smaug/bct/cfg2inc.sh34
-rw-r--r--src/mainboard/google/smaug/bct/emmc.cfg16
-rw-r--r--src/mainboard/google/smaug/bct/jtag.cfg16
-rw-r--r--src/mainboard/google/smaug/bct/odmdata.cfg1
-rw-r--r--src/mainboard/google/smaug/bct/sdram-samsung-204.cfg958
-rw-r--r--src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc476
-rw-r--r--src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc476
-rw-r--r--src/mainboard/google/smaug/bct/sdram-unused.inc4
-rw-r--r--src/mainboard/google/smaug/bct/spi.cfg16
-rw-r--r--src/mainboard/google/smaug/boardid.c43
-rw-r--r--src/mainboard/google/smaug/bootblock.c130
-rw-r--r--src/mainboard/google/smaug/chromeos.c111
-rw-r--r--src/mainboard/google/smaug/devicetree.cb53
-rw-r--r--src/mainboard/google/smaug/gpio.h72
-rw-r--r--src/mainboard/google/smaug/mainboard.c231
-rw-r--r--src/mainboard/google/smaug/memlayout.ld6
-rw-r--r--src/mainboard/google/smaug/pmic.c112
-rw-r--r--src/mainboard/google/smaug/pmic.h79
-rw-r--r--src/mainboard/google/smaug/reset.c30
-rw-r--r--src/mainboard/google/smaug/romstage.c57
-rw-r--r--src/mainboard/google/smaug/sdram_configs.c54
25 files changed, 3168 insertions, 0 deletions
diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig
new file mode 100644
index 0000000000..e96c7c6b82
--- /dev/null
+++ b/src/mainboard/google/smaug/Kconfig
@@ -0,0 +1,109 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+if BOARD_GOOGLE_SMAUG
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ID_AUTO
+ select BOARD_ROMSIZE_KB_16384
+ select CHROMEOS_VBNV_EC
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_I2C
+ select EC_GOOGLE_CHROMEEC_I2C_PROTO3
+ select EC_SOFTWARE_SYNC
+ select MAINBOARD_DO_NATIVE_VGA_INIT
+ select SPI_FLASH
+ select SOC_NVIDIA_TEGRA210
+ select MAINBOARD_DO_DSI_INIT
+ select MAINBOARD_HAS_BOOTBLOCK_INIT
+ select MAINBOARD_HAS_CHROMEOS
+ select VIRTUAL_DEV_SWITCH
+ select RAM_CODE_SUPPORT
+
+config MAINBOARD_DIR
+ string
+ default google/smaug
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Smaug"
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+choice
+ prompt "BCT boot media"
+ default SMAUG_BCT_CFG_SPI
+ help
+ Which boot media to configure the BCT for.
+
+config SMAUG_BCT_CFG_SPI
+ bool "SPI"
+ help
+ Configure the BCT for booting from SPI.
+
+config SMAUG_BCT_CFG_EMMC
+ bool "eMMC"
+ help
+ Configure the BCT for booting from eMMC.
+
+endchoice
+
+config BOOT_MEDIA_SPI_BUS
+ int "SPI bus with boot media ROM"
+ range 1 7
+ depends on SMAUG_BCT_CFG_SPI
+ default 7
+ help
+ Which SPI bus the boot media is connected to.
+
+config BOOT_MEDIA_SPI_CHIP_SELECT
+ int "Chip select for SPI boot media"
+ range 0 3
+ depends on SMAUG_BCT_CFG_SPI
+ default 0
+ help
+ Which chip select to use for boot media.
+
+# For smaug, we are using vboot2. Thus, index for stages:
+# VBOOT_ROMSTAGE_INDEX -> Use default value of 0x2
+# VBOOT_RAMSTAGE_INDEX -> Use 0x3
+config VBOOT_BL31_INDEX
+ hex
+ default 0x4
+
+config VBOOT_RAMSTAGE_INDEX
+ hex
+ default 0x3
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x2
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x20
+
+config EC_GOOGLE_CHROMEEC_I2C_BUS
+ hex
+ default 1
+
+endif # BOARD_GOOGLE_SMAUG
diff --git a/src/mainboard/google/smaug/Kconfig.name b/src/mainboard/google/smaug/Kconfig.name
new file mode 100644
index 0000000000..7f83a3a557
--- /dev/null
+++ b/src/mainboard/google/smaug/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_SMAUG
+ bool "Smaug"
diff --git a/src/mainboard/google/smaug/Makefile.inc b/src/mainboard/google/smaug/Makefile.inc
new file mode 100644
index 0000000000..1e84d54cf7
--- /dev/null
+++ b/src/mainboard/google/smaug/Makefile.inc
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+# Add a handler for BCT config files
+$(call add-special-class,bct-cfg)
+bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
+
+$(obj)/generated/bct.cfg:
+ @printf " CAT $(subst $(obj)/,,$(@))\n"
+ cat $^ > $@
+
+subdirs-y += bct
+
+bootblock-y += bootblock.c
+bootblock-y += pmic.c
+bootblock-y += reset.c
+
+verstage-y += chromeos.c
+verstage-y += reset.c
+
+romstage-y += chromeos.c
+romstage-y += pmic.c
+romstage-y += reset.c
+romstage-y += romstage.c
+romstage-y += sdram_configs.c
+
+ramstage-y += chromeos.c
+ramstage-y += boardid.c
+ramstage-y += mainboard.c
+ramstage-y += reset.c
+ramstage-y += pmic.c
+
+bootblock-y += memlayout.ld
+romstage-y += memlayout.ld
+ramstage-y += memlayout.ld
+verstage-y += memlayout.ld
diff --git a/src/mainboard/google/smaug/bct/Makefile.inc b/src/mainboard/google/smaug/bct/Makefile.inc
new file mode 100644
index 0000000000..74ff385a46
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/Makefile.inc
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2015 Google Inc.
+## Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+bct-cfg-$(CONFIG_SMAUG_BCT_CFG_EMMC) += emmc.cfg
+bct-cfg-$(CONFIG_SMAUG_BCT_CFG_SPI) += spi.cfg
+bct-cfg-y += odmdata.cfg
+bct-cfg-y += jtag.cfg
+#NOTE: When full LPDDR4 SDRAM config is done in romstage, remove this
+bct-cfg-$(CONFIG_BOOTROM_SDRAM_INIT) += sdram-samsung-204.cfg
+
+# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
+# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
+# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage.
diff --git a/src/mainboard/google/smaug/bct/cfg2inc.sh b/src/mainboard/google/smaug/bct/cfg2inc.sh
new file mode 100644
index 0000000000..cfa670925e
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/cfg2inc.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2015 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+
+bct_cfg2inc() {
+ local in_file="$1"
+ local out_file="$2"
+ echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}"
+ # Note currently we can only handle DDR3 type memory, even in C
+ # implementation.
+ sed "/^#.*$/d; s/^SDRAM.0./ /; s/\r$//; s/;$/,/;" \
+ "${in_file}" >> "${out_file}"
+ echo "}," >>"${out_file}"
+}
+
+for file in $@; do
+ echo "Generating $file => ${file%cfg}inc..."
+ bct_cfg2inc "${file}" "${file%cfg}inc"
+done
diff --git a/src/mainboard/google/smaug/bct/emmc.cfg b/src/mainboard/google/smaug/bct/emmc.cfg
new file mode 100644
index 0000000000..13ee04716f
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/emmc.cfg
@@ -0,0 +1,16 @@
+# Copyright 2015 Google Inc. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00210001;
+BlockSize = 0x00004000;
+PageSize = 0x00000200;
+PartitionSize = 0x01000000;
+
+#
+# T210 bct only supports one boot device
+#
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;
diff --git a/src/mainboard/google/smaug/bct/jtag.cfg b/src/mainboard/google/smaug/bct/jtag.cfg
new file mode 100644
index 0000000000..4f2c36c223
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/jtag.cfg
@@ -0,0 +1,16 @@
+#
+# Set JtagCtrl to 1 to reenable Jtag
+#
+JtagCtrl = 0;
+#
+# Fill in chip unique id
+#
+# ChipUid can be found by running tegrarcm in tegra recovery mode
+# (also hooking up A-A USB cable) and looking for console output
+# on line starting with "Chip UID:"
+#
+# Command example:
+# $ sudo tegrarcm --bct=/build/foster/firmware/bct/board.bct --bootloader=/build/foster/firmware/u-boot.bin --loadaddr=0x80108000
+# Where board.bct and u-boot.bin do not have to be prebuilt.
+#
+ChipUid = 0x00000000000000000000000000000000;
diff --git a/src/mainboard/google/smaug/bct/odmdata.cfg b/src/mainboard/google/smaug/bct/odmdata.cfg
new file mode 100644
index 0000000000..45648af315
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/odmdata.cfg
@@ -0,0 +1 @@
+OdmData = 0x00294000;
diff --git a/src/mainboard/google/smaug/bct/sdram-samsung-204.cfg b/src/mainboard/google/smaug/bct/sdram-samsung-204.cfg
new file mode 100644
index 0000000000..9bf9c97240
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/sdram-samsung-204.cfg
@@ -0,0 +1,958 @@
+# Do not edit. Generated by t210_emc_reg_tool_P975 V9.7.5. Command:
+# t210_emc_reg_tool_P975 -i Samsung_K4F2E304HA-MGCH_3GB.par 4.90196078431372549019 -dram_board_cfg 40
+# -dbi_rd_en 1 -data_bus_to_0 1 -fly_by_time_ps 1717 -t T210DSC_TBKV_A44_P5.xlsm_BKV.txt
+# -o T210_A44_R1_LP4_DSC_204Mhz.cfg
+# Parameter file: Samsung_K4F2E304HA-MGCH_3GB.par, tck = 4.90 ns (204.00 MHz)
+SDRAM[2].MemoryType = NvBootMemoryType_LpDdr4;
+SDRAM[2].PllMInputDivider = 0x00000001;
+SDRAM[2].PllMFeedbackDivider = 0x00000022;
+SDRAM[2].PllMStableTime = 0x0000012c;
+SDRAM[2].PllMSetupControl = 0x00000000;
+SDRAM[2].PllMPostDivider = 0x00000000;
+SDRAM[2].PllMKCP = 0x00000000;
+SDRAM[2].PllMKVCO = 0x00000000;
+SDRAM[2].EmcBctSpare0 = 0x00000000;
+SDRAM[2].EmcBctSpare1 = 0x00000000;
+SDRAM[2].EmcBctSpare2 = 0x00000000;
+SDRAM[2].EmcBctSpare3 = 0x00000000;
+SDRAM[2].EmcBctSpare4 = 0x7001bc3c;
+SDRAM[2].EmcBctSpare5 = 0x00000032;
+SDRAM[2].EmcBctSpare6 = 0x7001b404;
+SDRAM[2].EmcBctSpare7 = 0x76342501;
+SDRAM[2].EmcBctSpare8 = 0x7000e6c8;
+SDRAM[2].EmcBctSpare9 = 0x00000000;
+SDRAM[2].EmcBctSpare10 = 0x00000000;
+SDRAM[2].EmcBctSpare11 = 0x00000000;
+SDRAM[2].EmcBctSpare12 = 0x7001bc3c;
+SDRAM[2].EmcBctSpare13 = 0x00000033;
+SDRAM[2].EmcClockSource = 0x40188002;
+SDRAM[2].EmcClockSourceDll = 0x40000000;
+SDRAM[2].ClkRstControllerPllmMisc2Override = 0x00000000;
+SDRAM[2].ClkRstControllerPllmMisc2OverrideEnable = 0x00000000;
+SDRAM[2].ClearClk2Mc1 = 0x00000000;
+SDRAM[2].EmcAutoCalInterval = 0x001fffff;
+SDRAM[2].EmcAutoCalConfig = 0xa01a51d8;
+SDRAM[2].EmcAutoCalConfig2 = 0x05500000;
+SDRAM[2].EmcAutoCalConfig3 = 0x00770000;
+SDRAM[2].EmcAutoCalConfig4 = 0x00770000;
+SDRAM[2].EmcAutoCalConfig5 = 0x00770000;
+SDRAM[2].EmcAutoCalConfig6 = 0x00770000;
+SDRAM[2].EmcAutoCalConfig7 = 0x00770000;
+SDRAM[2].EmcAutoCalConfig8 = 0x00770000;
+SDRAM[2].EmcAutoCalVrefSel0 = 0xb3afa6a6;
+SDRAM[2].EmcAutoCalVrefSel1 = 0x00009e3c;
+SDRAM[2].EmcAutoCalChannel = 0xc1e00303;
+SDRAM[2].EmcPmacroAutocalCfg0 = 0x04040404;
+SDRAM[2].EmcPmacroAutocalCfg1 = 0x04040404;
+SDRAM[2].EmcPmacroAutocalCfg2 = 0x00000000;
+SDRAM[2].EmcPmacroRxTerm = 0x1f1f1f1f;
+SDRAM[2].EmcPmacroDqTxDrv = 0x1f1f1f1f;
+SDRAM[2].EmcPmacroCaTxDrv = 0x1f1f1f1f;
+SDRAM[2].EmcPmacroCmdTxDrv = 0x00001f1f;
+SDRAM[2].EmcPmacroAutocalCfgCommon = 0x00000804;
+SDRAM[2].EmcPmacroZctrl = 0x00000550;
+SDRAM[2].EmcAutoCalWait = 0x000001a1;
+SDRAM[2].EmcXm2CompPadCtrl = 0x00000032;
+SDRAM[2].EmcXm2CompPadCtrl2 = 0x00000000;
+SDRAM[2].EmcXm2CompPadCtrl3 = 0x00000000;
+SDRAM[2].EmcAdrCfg = 0x00000001;
+SDRAM[2].EmcPinProgramWait = 0x00000002;
+SDRAM[2].EmcPinExtraWait = 0x00000000;
+SDRAM[2].EmcPinGpioEn = 0x00000003;
+SDRAM[2].EmcPinGpio = 0x00000003;
+SDRAM[2].EmcTimingControlWait = 0x0000001e;
+SDRAM[2].EmcRc = 0x0000000d;
+SDRAM[2].EmcRfc = 0x00000025;
+SDRAM[2].EmcRfcPb = 0x00000013;
+SDRAM[2].EmcRefctrl2 = 0x00000000;
+SDRAM[2].EmcRfcSlr = 0x00000000;
+SDRAM[2].EmcRas = 0x00000009;
+SDRAM[2].EmcRp = 0x00000004;
+SDRAM[2].EmcR2r = 0x00000000;
+SDRAM[2].EmcW2w = 0x00000000;
+SDRAM[2].EmcR2w = 0x0000000b;
+SDRAM[2].EmcW2r = 0x0000000d;
+SDRAM[2].EmcR2p = 0x00000008;
+SDRAM[2].EmcW2p = 0x0000000b;
+SDRAM[2].EmcTppd = 0x00000004;
+SDRAM[2].EmcCcdmw = 0x00000020;
+SDRAM[2].EmcRdRcd = 0x00000006;
+SDRAM[2].EmcWrRcd = 0x00000006;
+SDRAM[2].EmcRrd = 0x00000006;
+SDRAM[2].EmcRext = 0x00000003;
+SDRAM[2].EmcWext = 0x00000000;
+SDRAM[2].EmcWdv = 0x00000004;
+SDRAM[2].EmcWdvChk = 0x00000006;
+SDRAM[2].EmcWsv = 0x00000002;
+SDRAM[2].EmcWev = 0x00000000;
+SDRAM[2].EmcWdvMask = 0x00000004;
+SDRAM[2].EmcWsDuration = 0x00000008;
+SDRAM[2].EmcWeDuration = 0x0000000d;
+SDRAM[2].EmcQUse = 0x00000005;
+SDRAM[2].EmcQuseWidth = 0x00000006;
+SDRAM[2].EmcIbdly = 0x00000000;
+SDRAM[2].EmcObdly = 0x00000000;
+SDRAM[2].EmcEInput = 0x00000002;
+SDRAM[2].EmcEInputDuration = 0x0000000d;
+SDRAM[2].EmcPutermExtra = 0x00000002;
+SDRAM[2].EmcPutermWidth = 0x0000000b;
+SDRAM[2].EmcQRst = 0x00010000;
+SDRAM[2].EmcQSafe = 0x00000012;
+SDRAM[2].EmcRdv = 0x00000014;
+SDRAM[2].EmcRdvMask = 0x00000016;
+SDRAM[2].EmcRdvEarly = 0x00000012;
+SDRAM[2].EmcRdvEarlyMask = 0x00000014;
+SDRAM[2].EmcQpop = 0x0000000a;
+SDRAM[2].EmcRefresh = 0x00000304;
+SDRAM[2].EmcBurstRefreshNum = 0x00000000;
+SDRAM[2].EmcPreRefreshReqCnt = 0x000000c1;
+SDRAM[2].EmcPdEx2Wr = 0x00000008;
+SDRAM[2].EmcPdEx2Rd = 0x00000008;
+SDRAM[2].EmcPChg2Pden = 0x00000003;
+SDRAM[2].EmcAct2Pden = 0x00000003;
+SDRAM[2].EmcAr2Pden = 0x00000003;
+SDRAM[2].EmcRw2Pden = 0x00000012;
+SDRAM[2].EmcCke2Pden = 0x00000005;
+SDRAM[2].EmcPdex2Cke = 0x00000002;
+SDRAM[2].EmcPdex2Mrr = 0x0000000d;
+SDRAM[2].EmcTxsr = 0x00000027;
+SDRAM[2].EmcTxsrDll = 0x00000027;
+SDRAM[2].EmcTcke = 0x00000005;
+SDRAM[2].EmcTckesr = 0x00000005;
+SDRAM[2].EmcTpd = 0x00000004;
+SDRAM[2].EmcTfaw = 0x00000009;
+SDRAM[2].EmcTrpab = 0x00000005;
+SDRAM[2].EmcTClkStable = 0x00000003;
+SDRAM[2].EmcTClkStop = 0x00000009;
+SDRAM[2].EmcTRefBw = 0x0000031c;
+SDRAM[2].EmcFbioCfg5 = 0x9160a00d;
+SDRAM[2].EmcFbioCfg7 = 0x00003bbf;
+SDRAM[2].EmcFbioCfg8 = 0x0cf30000;
+SDRAM[2].EmcCmdMappingCmd0_0 = 0x07050203;
+SDRAM[2].EmcCmdMappingCmd0_1 = 0x06041b1c;
+SDRAM[2].EmcCmdMappingCmd0_2 = 0x05252523;
+SDRAM[2].EmcCmdMappingCmd1_0 = 0x1e0d0b0a;
+SDRAM[2].EmcCmdMappingCmd1_1 = 0x240c091d;
+SDRAM[2].EmcCmdMappingCmd1_2 = 0x04262608;
+SDRAM[2].EmcCmdMappingCmd2_0 = 0x051b0302;
+SDRAM[2].EmcCmdMappingCmd2_1 = 0x0604231c;
+SDRAM[2].EmcCmdMappingCmd2_2 = 0x09252507;
+SDRAM[2].EmcCmdMappingCmd3_0 = 0x0c0b0d0a;
+SDRAM[2].EmcCmdMappingCmd3_1 = 0x08091e1d;
+SDRAM[2].EmcCmdMappingCmd3_2 = 0x08262624;
+SDRAM[2].EmcCmdMappingByte = 0x0a070623;
+SDRAM[2].EmcFbioSpare = 0x00000012;
+SDRAM[2].EmcCfgRsv = 0xff00ff00;
+SDRAM[2].EmcMrs = 0x00000000;
+SDRAM[2].EmcEmrs = 0x00000000;
+SDRAM[2].EmcEmrs2 = 0x00000000;
+SDRAM[2].EmcEmrs3 = 0x00000000;
+SDRAM[2].EmcMrw1 = 0x08010004;
+SDRAM[2].EmcMrw2 = 0x08020000;
+SDRAM[2].EmcMrw3 = 0x080d0000;
+SDRAM[2].EmcMrw4 = 0xc0000000;
+SDRAM[2].EmcMrw6 = 0x08037171;
+SDRAM[2].EmcMrw8 = 0x080b0000;
+SDRAM[2].EmcMrw9 = 0x0c0e6b6b;
+SDRAM[2].EmcMrw10 = 0x00000000;
+SDRAM[2].EmcMrw12 = 0x0c0d0808;
+SDRAM[2].EmcMrw13 = 0x0c0d0000;
+SDRAM[2].EmcMrw14 = 0x08161414;
+SDRAM[2].EmcMrwExtra = 0x08010004;
+SDRAM[2].EmcWarmBootMrwExtra = 0x08110000;
+SDRAM[2].EmcWarmBootExtraModeRegWriteEnable = 0x00000001;
+SDRAM[2].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[2].EmcMrwResetCommand = 0x00000000;
+SDRAM[2].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[2].EmcMrsWaitCnt = 0x00cc0015;
+SDRAM[2].EmcMrsWaitCnt2 = 0x0033000a;
+SDRAM[2].EmcCfg = 0xf3200000;
+SDRAM[2].EmcCfg2 = 0x00110805;
+SDRAM[2].EmcCfgPipe = 0x0fff0fff;
+SDRAM[2].EmcCfgPipeClk = 0x00000000;
+SDRAM[2].EmcFdpdCtrlCmdNoRamp = 0x00000001;
+SDRAM[2].EmcCfgUpdate = 0x70000301;
+SDRAM[2].EmcDbg = 0x01000c00;
+SDRAM[2].EmcDbgWriteMux = 0x00000001;
+SDRAM[2].EmcCmdQ = 0x10004408;
+SDRAM[2].EmcMc2EmcQ = 0x06000404;
+SDRAM[2].EmcDynSelfRefControl = 0x80000713;
+SDRAM[2].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[2].EmcCfgDigDll = 0x002c00a0;
+SDRAM[2].EmcCfgDigDll_1 = 0x00003701;
+SDRAM[2].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[2].EmcDevSelect = 0x00000000;
+SDRAM[2].EmcSelDpdCtrl = 0x00040008;
+SDRAM[2].EmcFdpdCtrlDq = 0x8020221f;
+SDRAM[2].EmcFdpdCtrlCmd = 0x0220f40f;
+SDRAM[2].EmcPmacroIbVrefDq_0 = 0x28282828;
+SDRAM[2].EmcPmacroIbVrefDq_1 = 0x28282828;
+SDRAM[2].EmcPmacroIbVrefDqs_0 = 0x11111111;
+SDRAM[2].EmcPmacroIbVrefDqs_1 = 0x11111111;
+SDRAM[2].EmcPmacroIbRxrt = 0x000000be;
+SDRAM[2].EmcCfgPipe1 = 0x0fff0fff;
+SDRAM[2].EmcCfgPipe2 = 0x0fff0fff;
+SDRAM[2].EmcPmacroQuseDdllRank0_0 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank0_1 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank0_2 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank0_3 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank0_4 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank0_5 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank1_0 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank1_1 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank1_2 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank1_3 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank1_4 = 0x00000000;
+SDRAM[2].EmcPmacroQuseDdllRank1_5 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank0_0 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank0_1 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank0_2 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank0_3 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank0_4 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank0_5 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank1_0 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank1_1 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank1_2 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank1_3 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank1_4 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqRank1_5 = 0x00000000;
+SDRAM[2].EmcPmacroObDdllLongDqsRank0_0 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank0_1 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank0_2 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank0_3 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank0_4 = 0x00090009;
+SDRAM[2].EmcPmacroObDdllLongDqsRank0_5 = 0x00090009;
+SDRAM[2].EmcPmacroObDdllLongDqsRank1_0 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank1_1 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank1_2 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank1_3 = 0x00320032;
+SDRAM[2].EmcPmacroObDdllLongDqsRank1_4 = 0x00090009;
+SDRAM[2].EmcPmacroObDdllLongDqsRank1_5 = 0x00090009;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank0_0 = 0x00280028;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank0_1 = 0x00280028;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank0_2 = 0x00280028;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank0_3 = 0x00280028;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank1_0 = 0x00280028;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank1_1 = 0x00280028;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank1_2 = 0x00280028;
+SDRAM[2].EmcPmacroIbDdllLongDqsRank1_3 = 0x00280028;
+SDRAM[2].EmcPmacroDdllLongCmd_0 = 0x00000000;
+SDRAM[2].EmcPmacroDdllLongCmd_1 = 0x00000000;
+SDRAM[2].EmcPmacroDdllLongCmd_2 = 0x00000000;
+SDRAM[2].EmcPmacroDdllLongCmd_3 = 0x00000000;
+SDRAM[2].EmcPmacroDdllLongCmd_4 = 0x00000000;
+SDRAM[2].EmcPmacroDdllShortCmd_0 = 0x00000000;
+SDRAM[2].EmcPmacroDdllShortCmd_1 = 0x00000000;
+SDRAM[2].EmcPmacroDdllShortCmd_2 = 0x00000000;
+SDRAM[2].WarmBootWait = 0x00000001;
+SDRAM[2].EmcOdtWrite = 0x00000000;
+SDRAM[2].EmcZcalInterval = 0x00064000;
+SDRAM[2].EmcZcalWaitCnt = 0x000900cc;
+SDRAM[2].EmcZcalMrwCmd = 0x0051004f;
+SDRAM[2].EmcMrsResetDll = 0x00000000;
+SDRAM[2].EmcZcalInitDev0 = 0x80000001;
+SDRAM[2].EmcZcalInitDev1 = 0x40000001;
+SDRAM[2].EmcZcalInitWait = 0x00000001;
+SDRAM[2].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[2].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[2].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[2].EmcZqCalLpDdr4WarmBoot = 0x00000001;
+SDRAM[2].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[2].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[2].EmcMrsResetDllWait = 0x00000000;
+SDRAM[2].EmcMrsExtra = 0x00000000;
+SDRAM[2].EmcWarmBootMrsExtra = 0x00000000;
+SDRAM[2].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[2].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[2].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[2].EmcDdr2Wait = 0x00000000;
+SDRAM[2].EmcClkenOverride = 0x00000000;
+SDRAM[2].EmcExtraRefreshNum = 0x00000002;
+SDRAM[2].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[2].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[2].PmcVddpSel = 0x00000001;
+SDRAM[2].PmcVddpSelWait = 0x00000002;
+SDRAM[2].PmcDdrPwr = 0x0000000f;
+SDRAM[2].PmcDdrCfg = 0x20220100;
+SDRAM[2].PmcIoDpd3Req = 0x4bafffff;
+SDRAM[2].PmcIoDpd3ReqWait = 0x00000001;
+SDRAM[2].PmcIoDpd4ReqWait = 0x00000002;
+SDRAM[2].PmcRegShort = 0x00000000;
+SDRAM[2].PmcNoIoPower = 0x00000000;
+SDRAM[2].PmcDdrCntrlWait = 0x00000000;
+SDRAM[2].PmcDdrCntrl = 0x0007ff8b;
+SDRAM[2].EmcAcpdControl = 0x00000000;
+SDRAM[2].EmcSwizzleRank0Byte0 = 0x76342501;
+SDRAM[2].EmcSwizzleRank0Byte1 = 0x56243701;
+SDRAM[2].EmcSwizzleRank0Byte2 = 0x34267510;
+SDRAM[2].EmcSwizzleRank0Byte3 = 0x45763210;
+SDRAM[2].EmcSwizzleRank1Byte0 = 0x72345601;
+SDRAM[2].EmcSwizzleRank1Byte1 = 0x23456701;
+SDRAM[2].EmcSwizzleRank1Byte2 = 0x65427310;
+SDRAM[2].EmcSwizzleRank1Byte3 = 0x75432610;
+SDRAM[2].EmcTxdsrvttgen = 0x00000000;
+SDRAM[2].EmcDataBrlshft0 = 0x00249249;
+SDRAM[2].EmcDataBrlshft1 = 0x00249249;
+SDRAM[2].EmcDqsBrlshft0 = 0x00000000;
+SDRAM[2].EmcDqsBrlshft1 = 0x00000000;
+SDRAM[2].EmcCmdBrlshft0 = 0x00000000;
+SDRAM[2].EmcCmdBrlshft1 = 0x00000000;
+SDRAM[2].EmcCmdBrlshft2 = 0x00000012;
+SDRAM[2].EmcCmdBrlshft3 = 0x00000012;
+SDRAM[2].EmcQuseBrlshft0 = 0x00000000;
+SDRAM[2].EmcQuseBrlshft1 = 0x00000000;
+SDRAM[2].EmcQuseBrlshft2 = 0x00000000;
+SDRAM[2].EmcQuseBrlshft3 = 0x00000000;
+SDRAM[2].EmcDllCfg0 = 0x1f13412f;
+SDRAM[2].EmcDllCfg1 = 0x00010014;
+SDRAM[2].EmcPmcScratch1 = 0x4bafffff;
+SDRAM[2].EmcPmcScratch2 = 0x7fffffff;
+SDRAM[2].EmcPmcScratch3 = 0x4005d70b;
+SDRAM[2].EmcPmacroPadCfgCtrl = 0x00020000;
+SDRAM[2].EmcPmacroVttgenCtrl0 = 0x00030808;
+SDRAM[2].EmcPmacroVttgenCtrl1 = 0x00015000;
+SDRAM[2].EmcPmacroVttgenCtrl2 = 0x00101010;
+SDRAM[2].EmcPmacroBrickCtrlRfu1 = 0x00001600;
+SDRAM[2].EmcPmacroCmdBrickCtrlFdpd = 0x00000000;
+SDRAM[2].EmcPmacroBrickCtrlRfu2 = 0x00000000;
+SDRAM[2].EmcPmacroDataBrickCtrlFdpd = 0x00000000;
+SDRAM[2].EmcPmacroBgBiasCtrl0 = 0x00000030;
+SDRAM[2].EmcPmacroDataPadRxCtrl = 0x10050037;
+SDRAM[2].EmcPmacroCmdPadRxCtrl = 0x00000000;
+SDRAM[2].EmcPmacroDataRxTermMode = 0x00000010;
+SDRAM[2].EmcPmacroCmdRxTermMode = 0x00003000;
+SDRAM[2].EmcPmacroDataPadTxCtrl = 0x02000111;
+SDRAM[2].EmcPmacroCommonPadTxCtrl = 0x00000008;
+SDRAM[2].EmcPmacroCmdPadTxCtrl = 0x0a000000;
+SDRAM[2].EmcCfg3 = 0x00000040;
+SDRAM[2].EmcPmacroTxPwrd0 = 0x10000000;
+SDRAM[2].EmcPmacroTxPwrd1 = 0x08000000;
+SDRAM[2].EmcPmacroTxPwrd2 = 0x08000000;
+SDRAM[2].EmcPmacroTxPwrd3 = 0x08000000;
+SDRAM[2].EmcPmacroTxPwrd4 = 0x00000000;
+SDRAM[2].EmcPmacroTxPwrd5 = 0x00000000;
+SDRAM[2].EmcConfigSampleDelay = 0x00000020;
+SDRAM[2].EmcPmacroBrickMapping0 = 0x28190081;
+SDRAM[2].EmcPmacroBrickMapping1 = 0x44a53293;
+SDRAM[2].EmcPmacroBrickMapping2 = 0x76b76a5b;
+SDRAM[2].EmcPmacroTxSelClkSrc0 = 0x00000000;
+SDRAM[2].EmcPmacroTxSelClkSrc1 = 0x00000000;
+SDRAM[2].EmcPmacroTxSelClkSrc2 = 0x00000000;
+SDRAM[2].EmcPmacroTxSelClkSrc3 = 0x00000000;
+SDRAM[2].EmcPmacroTxSelClkSrc4 = 0x00000000;
+SDRAM[2].EmcPmacroTxSelClkSrc5 = 0x00000000;
+SDRAM[2].EmcPmacroDdllBypass = 0xefffefff;
+SDRAM[2].EmcPmacroDdllPwrd0 = 0xc0c0c0c0;
+SDRAM[2].EmcPmacroDdllPwrd1 = 0xc0c0c0c0;
+SDRAM[2].EmcPmacroDdllPwrd2 = 0xdcdcdcdc;
+SDRAM[2].EmcPmacroCmdCtrl0 = 0x0a0a0a0a;
+SDRAM[2].EmcPmacroCmdCtrl1 = 0x0a0a0a0a;
+SDRAM[2].EmcPmacroCmdCtrl2 = 0x0a0a0a0a;
+SDRAM[2].McEmemAdrCfg = 0x00000001;
+SDRAM[2].McEmemAdrCfgDev0 = 0x000d0302;
+SDRAM[2].McEmemAdrCfgDev1 = 0x000d0302;
+SDRAM[2].McEmemAdrCfgChannelMask = 0xffff2400;
+SDRAM[2].McEmemAdrCfgBankMask0 = 0x6e574400;
+SDRAM[2].McEmemAdrCfgBankMask1 = 0x39722800;
+SDRAM[2].McEmemAdrCfgBankMask2 = 0x4b9c1000;
+SDRAM[2].McEmemCfg = 0x00000c00;
+SDRAM[2].McEmemArbCfg = 0x08000001;
+SDRAM[2].McEmemArbOutstandingReq = 0x8000004c;
+SDRAM[2].McEmemArbRefpbHpCtrl = 0x000a1020;
+SDRAM[2].McEmemArbRefpbBankCtrl = 0x80001028;
+SDRAM[2].McEmemArbTimingRcd = 0x00000001;
+SDRAM[2].McEmemArbTimingRp = 0x00000000;
+SDRAM[2].McEmemArbTimingRc = 0x00000003;
+SDRAM[2].McEmemArbTimingRas = 0x00000001;
+SDRAM[2].McEmemArbTimingFaw = 0x00000002;
+SDRAM[2].McEmemArbTimingRrd = 0x00000001;
+SDRAM[2].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[2].McEmemArbTimingWap2Pre = 0x00000005;
+SDRAM[2].McEmemArbTimingR2R = 0x00000001;
+SDRAM[2].McEmemArbTimingW2W = 0x00000001;
+SDRAM[2].McEmemArbTimingR2W = 0x00000004;
+SDRAM[2].McEmemArbTimingW2R = 0x00000005;
+SDRAM[2].McEmemArbTimingRFCPB = 0x00000004;
+SDRAM[2].McEmemArbDaTurns = 0x02020000;
+SDRAM[2].McEmemArbDaCovers = 0x00030201;
+SDRAM[2].McEmemArbMisc0 = 0x71c30504;
+SDRAM[2].McEmemArbMisc1 = 0x70000f0f;
+SDRAM[2].McEmemArbMisc2 = 0x00000000;
+SDRAM[2].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[2].McEmemArbOverride = 0x10000000;
+SDRAM[2].McEmemArbOverride1 = 0x00000000;
+SDRAM[2].McEmemArbRsv = 0xff00ff00;
+SDRAM[2].McDaCfg0 = 0x00000001;
+SDRAM[2].McEmemArbTimingCcdmw = 0x00000008;
+SDRAM[2].McClkenOverride = 0x00008000;
+SDRAM[2].McStatControl = 0x00000000;
+SDRAM[2].McVideoProtectBom = 0xfff00000;
+SDRAM[2].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[2].McVideoProtectSizeMb = 0x00000000;
+SDRAM[2].McVideoProtectVprOverride = 0xe4bac343;
+SDRAM[2].McVideoProtectVprOverride1 = 0x00001ed3;
+SDRAM[2].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[2].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[2].McSecCarveoutBom = 0xfff00000;
+SDRAM[2].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[2].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[2].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[2].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1Bom = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1BomHi = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1Size128kb = 0x00000008;
+SDRAM[2].McGeneralizedCarveout1Access0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1Access1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1Access2 = 0x00300000;
+SDRAM[2].McGeneralizedCarveout1Access3 = 0x03000000;
+SDRAM[2].McGeneralizedCarveout1Access4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1ForceInternalAccess0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1ForceInternalAccess1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1ForceInternalAccess2 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1ForceInternalAccess3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1ForceInternalAccess4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout1Cfg0 = 0x04000c75;
+SDRAM[2].McGeneralizedCarveout2Bom = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2BomHi = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2Size128kb = 0x00000002;
+SDRAM[2].McGeneralizedCarveout2Access0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2Access1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2Access2 = 0x03000000;
+SDRAM[2].McGeneralizedCarveout2Access3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2Access4 = 0x00000300;
+SDRAM[2].McGeneralizedCarveout2ForceInternalAccess0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2ForceInternalAccess1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2ForceInternalAccess2 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2ForceInternalAccess3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2ForceInternalAccess4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout2Cfg0 = 0x0440167c;
+SDRAM[2].McGeneralizedCarveout3Bom = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3BomHi = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3Size128kb = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3Access0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3Access1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3Access2 = 0x03000000;
+SDRAM[2].McGeneralizedCarveout3Access3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3Access4 = 0x00000300;
+SDRAM[2].McGeneralizedCarveout3ForceInternalAccess0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3ForceInternalAccess1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3ForceInternalAccess2 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3ForceInternalAccess3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3ForceInternalAccess4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout3Cfg0 = 0x04401e7c;
+SDRAM[2].McGeneralizedCarveout4Bom = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4BomHi = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4Size128kb = 0x00000008;
+SDRAM[2].McGeneralizedCarveout4Access0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4Access1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4Access2 = 0x00300000;
+SDRAM[2].McGeneralizedCarveout4Access3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4Access4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4ForceInternalAccess0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4ForceInternalAccess1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout4Cfg0 = 0x04002442;
+SDRAM[2].McGeneralizedCarveout5Bom = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5BomHi = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5Size128kb = 0x00000008;
+SDRAM[2].McGeneralizedCarveout5Access0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5Access1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5Access2 = 0x00300000;
+SDRAM[2].McGeneralizedCarveout5Access3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5Access4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5ForceInternalAccess0 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5ForceInternalAccess1 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000;
+SDRAM[2].McGeneralizedCarveout5Cfg0 = 0x04002c42;
+SDRAM[2].EmcCaTrainingEnable = 0x00000000;
+SDRAM[2].SwizzleRankByteEncode = 0x0000002e;
+SDRAM[2].BootRomPatchControl = 0x00000000;
+SDRAM[2].BootRomPatchData = 0x00000000;
+SDRAM[2].McMtsCarveoutBom = 0xfff00000;
+SDRAM[2].McMtsCarveoutAdrHi = 0x00000000;
+SDRAM[2].McMtsCarveoutSizeMb = 0x00000000;
+SDRAM[2].McMtsCarveoutRegCtrl = 0x00000000;
+# Do not edit. Generated by t210_emc_reg_tool_P975 V9.7.5. Command:
+# t210_emc_reg_tool_P975 -i Samsung_K4F6E304HA-MGCH_4GB.par 4.90196078431372549019 -dram_board_cfg 40
+# -dbi_rd_en 1 -data_bus_to_0 1 -fly_by_time_ps 1717 -t T210DSC_TBKV_A44_P5.xlsm_BKV.txt
+# -o T210_A44_R1_LP4_DSC_4G_204Mhz.cfg
+# Parameter file: Samsung_K4F6E304HA-MGCH_4GB.par, tck = 4.90 ns (204.00 MHz)
+SDRAM[3].MemoryType = NvBootMemoryType_LpDdr4;
+SDRAM[3].PllMInputDivider = 0x00000001;
+SDRAM[3].PllMFeedbackDivider = 0x00000022;
+SDRAM[3].PllMStableTime = 0x0000012c;
+SDRAM[3].PllMSetupControl = 0x00000000;
+SDRAM[3].PllMPostDivider = 0x00000000;
+SDRAM[3].PllMKCP = 0x00000000;
+SDRAM[3].PllMKVCO = 0x00000000;
+SDRAM[3].EmcBctSpare0 = 0x00000000;
+SDRAM[3].EmcBctSpare1 = 0x00000000;
+SDRAM[3].EmcBctSpare2 = 0x00000000;
+SDRAM[3].EmcBctSpare3 = 0x00000000;
+SDRAM[3].EmcBctSpare4 = 0x7001bc3c;
+SDRAM[3].EmcBctSpare5 = 0x00000032;
+SDRAM[3].EmcBctSpare6 = 0x7001b404;
+SDRAM[3].EmcBctSpare7 = 0x76342501;
+SDRAM[3].EmcBctSpare8 = 0x7000e6c8;
+SDRAM[3].EmcBctSpare9 = 0x00000000;
+SDRAM[3].EmcBctSpare10 = 0x00000000;
+SDRAM[3].EmcBctSpare11 = 0x00000000;
+SDRAM[3].EmcBctSpare12 = 0x7001bc3c;
+SDRAM[3].EmcBctSpare13 = 0x00000033;
+SDRAM[3].EmcClockSource = 0x40188002;
+SDRAM[3].EmcClockSourceDll = 0x40000000;
+SDRAM[3].ClkRstControllerPllmMisc2Override = 0x00000000;
+SDRAM[3].ClkRstControllerPllmMisc2OverrideEnable = 0x00000000;
+SDRAM[3].ClearClk2Mc1 = 0x00000000;
+SDRAM[3].EmcAutoCalInterval = 0x001fffff;
+SDRAM[3].EmcAutoCalConfig = 0xa01a51d8;
+SDRAM[3].EmcAutoCalConfig2 = 0x05500000;
+SDRAM[3].EmcAutoCalConfig3 = 0x00770000;
+SDRAM[3].EmcAutoCalConfig4 = 0x00770000;
+SDRAM[3].EmcAutoCalConfig5 = 0x00770000;
+SDRAM[3].EmcAutoCalConfig6 = 0x00770000;
+SDRAM[3].EmcAutoCalConfig7 = 0x00770000;
+SDRAM[3].EmcAutoCalConfig8 = 0x00770000;
+SDRAM[3].EmcAutoCalVrefSel0 = 0xb3afa6a6;
+SDRAM[3].EmcAutoCalVrefSel1 = 0x00009e3c;
+SDRAM[3].EmcAutoCalChannel = 0xc1e00303;
+SDRAM[3].EmcPmacroAutocalCfg0 = 0x04040404;
+SDRAM[3].EmcPmacroAutocalCfg1 = 0x04040404;
+SDRAM[3].EmcPmacroAutocalCfg2 = 0x00000000;
+SDRAM[3].EmcPmacroRxTerm = 0x1f1f1f1f;
+SDRAM[3].EmcPmacroDqTxDrv = 0x1f1f1f1f;
+SDRAM[3].EmcPmacroCaTxDrv = 0x1f1f1f1f;
+SDRAM[3].EmcPmacroCmdTxDrv = 0x00001f1f;
+SDRAM[3].EmcPmacroAutocalCfgCommon = 0x00000804;
+SDRAM[3].EmcPmacroZctrl = 0x00000550;
+SDRAM[3].EmcAutoCalWait = 0x000001a1;
+SDRAM[3].EmcXm2CompPadCtrl = 0x00000032;
+SDRAM[3].EmcXm2CompPadCtrl2 = 0x00000000;
+SDRAM[3].EmcXm2CompPadCtrl3 = 0x00000000;
+SDRAM[3].EmcAdrCfg = 0x00000001;
+SDRAM[3].EmcPinProgramWait = 0x00000002;
+SDRAM[3].EmcPinExtraWait = 0x00000000;
+SDRAM[3].EmcPinGpioEn = 0x00000003;
+SDRAM[3].EmcPinGpio = 0x00000003;
+SDRAM[3].EmcTimingControlWait = 0x0000001e;
+SDRAM[3].EmcRc = 0x0000000d;
+SDRAM[3].EmcRfc = 0x00000025;
+SDRAM[3].EmcRfcPb = 0x00000013;
+SDRAM[3].EmcRefctrl2 = 0x00000000;
+SDRAM[3].EmcRfcSlr = 0x00000000;
+SDRAM[3].EmcRas = 0x00000009;
+SDRAM[3].EmcRp = 0x00000004;
+SDRAM[3].EmcR2r = 0x00000000;
+SDRAM[3].EmcW2w = 0x00000000;
+SDRAM[3].EmcR2w = 0x0000000b;
+SDRAM[3].EmcW2r = 0x0000000d;
+SDRAM[3].EmcR2p = 0x00000008;
+SDRAM[3].EmcW2p = 0x0000000b;
+SDRAM[3].EmcTppd = 0x00000004;
+SDRAM[3].EmcCcdmw = 0x00000020;
+SDRAM[3].EmcRdRcd = 0x00000006;
+SDRAM[3].EmcWrRcd = 0x00000006;
+SDRAM[3].EmcRrd = 0x00000006;
+SDRAM[3].EmcRext = 0x00000003;
+SDRAM[3].EmcWext = 0x00000000;
+SDRAM[3].EmcWdv = 0x00000004;
+SDRAM[3].EmcWdvChk = 0x00000006;
+SDRAM[3].EmcWsv = 0x00000002;
+SDRAM[3].EmcWev = 0x00000000;
+SDRAM[3].EmcWdvMask = 0x00000004;
+SDRAM[3].EmcWsDuration = 0x00000008;
+SDRAM[3].EmcWeDuration = 0x0000000d;
+SDRAM[3].EmcQUse = 0x00000005;
+SDRAM[3].EmcQuseWidth = 0x00000006;
+SDRAM[3].EmcIbdly = 0x00000000;
+SDRAM[3].EmcObdly = 0x00000000;
+SDRAM[3].EmcEInput = 0x00000002;
+SDRAM[3].EmcEInputDuration = 0x0000000d;
+SDRAM[3].EmcPutermExtra = 0x00000002;
+SDRAM[3].EmcPutermWidth = 0x0000000b;
+SDRAM[3].EmcQRst = 0x00010000;
+SDRAM[3].EmcQSafe = 0x00000012;
+SDRAM[3].EmcRdv = 0x00000014;
+SDRAM[3].EmcRdvMask = 0x00000016;
+SDRAM[3].EmcRdvEarly = 0x00000012;
+SDRAM[3].EmcRdvEarlyMask = 0x00000014;
+SDRAM[3].EmcQpop = 0x0000000a;
+SDRAM[3].EmcRefresh = 0x00000304;
+SDRAM[3].EmcBurstRefreshNum = 0x00000000;
+SDRAM[3].EmcPreRefreshReqCnt = 0x000000c1;
+SDRAM[3].EmcPdEx2Wr = 0x00000008;
+SDRAM[3].EmcPdEx2Rd = 0x00000008;
+SDRAM[3].EmcPChg2Pden = 0x00000003;
+SDRAM[3].EmcAct2Pden = 0x00000003;
+SDRAM[3].EmcAr2Pden = 0x00000003;
+SDRAM[3].EmcRw2Pden = 0x00000012;
+SDRAM[3].EmcCke2Pden = 0x00000005;
+SDRAM[3].EmcPdex2Cke = 0x00000002;
+SDRAM[3].EmcPdex2Mrr = 0x0000000d;
+SDRAM[3].EmcTxsr = 0x00000027;
+SDRAM[3].EmcTxsrDll = 0x00000027;
+SDRAM[3].EmcTcke = 0x00000005;
+SDRAM[3].EmcTckesr = 0x00000005;
+SDRAM[3].EmcTpd = 0x00000004;
+SDRAM[3].EmcTfaw = 0x00000009;
+SDRAM[3].EmcTrpab = 0x00000005;
+SDRAM[3].EmcTClkStable = 0x00000003;
+SDRAM[3].EmcTClkStop = 0x00000009;
+SDRAM[3].EmcTRefBw = 0x0000031c;
+SDRAM[3].EmcFbioCfg5 = 0x9160a00d;
+SDRAM[3].EmcFbioCfg7 = 0x00003bbf;
+SDRAM[3].EmcFbioCfg8 = 0x0cf30000;
+SDRAM[3].EmcCmdMappingCmd0_0 = 0x07050203;
+SDRAM[3].EmcCmdMappingCmd0_1 = 0x06041b1c;
+SDRAM[3].EmcCmdMappingCmd0_2 = 0x05252523;
+SDRAM[3].EmcCmdMappingCmd1_0 = 0x1e0d0b0a;
+SDRAM[3].EmcCmdMappingCmd1_1 = 0x240c091d;
+SDRAM[3].EmcCmdMappingCmd1_2 = 0x04262608;
+SDRAM[3].EmcCmdMappingCmd2_0 = 0x051b0302;
+SDRAM[3].EmcCmdMappingCmd2_1 = 0x0604231c;
+SDRAM[3].EmcCmdMappingCmd2_2 = 0x09252507;
+SDRAM[3].EmcCmdMappingCmd3_0 = 0x0c0b0d0a;
+SDRAM[3].EmcCmdMappingCmd3_1 = 0x08091e1d;
+SDRAM[3].EmcCmdMappingCmd3_2 = 0x08262624;
+SDRAM[3].EmcCmdMappingByte = 0x0a070623;
+SDRAM[3].EmcFbioSpare = 0x00000012;
+SDRAM[3].EmcCfgRsv = 0xff00ff00;
+SDRAM[3].EmcMrs = 0x00000000;
+SDRAM[3].EmcEmrs = 0x00000000;
+SDRAM[3].EmcEmrs2 = 0x00000000;
+SDRAM[3].EmcEmrs3 = 0x00000000;
+SDRAM[3].EmcMrw1 = 0x08010004;
+SDRAM[3].EmcMrw2 = 0x08020000;
+SDRAM[3].EmcMrw3 = 0x080d0000;
+SDRAM[3].EmcMrw4 = 0xc0000000;
+SDRAM[3].EmcMrw6 = 0x08037171;
+SDRAM[3].EmcMrw8 = 0x080b0000;
+SDRAM[3].EmcMrw9 = 0x0c0e6b6b;
+SDRAM[3].EmcMrw10 = 0x00000000;
+SDRAM[3].EmcMrw12 = 0x0c0d0808;
+SDRAM[3].EmcMrw13 = 0x0c0d0000;
+SDRAM[3].EmcMrw14 = 0x08161414;
+SDRAM[3].EmcMrwExtra = 0x08010004;
+SDRAM[3].EmcWarmBootMrwExtra = 0x08110000;
+SDRAM[3].EmcWarmBootExtraModeRegWriteEnable = 0x00000001;
+SDRAM[3].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[3].EmcMrwResetCommand = 0x00000000;
+SDRAM[3].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[3].EmcMrsWaitCnt = 0x00cc0015;
+SDRAM[3].EmcMrsWaitCnt2 = 0x0033000a;
+SDRAM[3].EmcCfg = 0xf3200000;
+SDRAM[3].EmcCfg2 = 0x00110805;
+SDRAM[3].EmcCfgPipe = 0x0fff0fff;
+SDRAM[3].EmcCfgPipeClk = 0x00000000;
+SDRAM[3].EmcFdpdCtrlCmdNoRamp = 0x00000001;
+SDRAM[3].EmcCfgUpdate = 0x70000301;
+SDRAM[3].EmcDbg = 0x01000c00;
+SDRAM[3].EmcDbgWriteMux = 0x00000001;
+SDRAM[3].EmcCmdQ = 0x10004408;
+SDRAM[3].EmcMc2EmcQ = 0x06000404;
+SDRAM[3].EmcDynSelfRefControl = 0x80000713;
+SDRAM[3].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[3].EmcCfgDigDll = 0x002c00a0;
+SDRAM[3].EmcCfgDigDll_1 = 0x00003701;
+SDRAM[3].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[3].EmcDevSelect = 0x00000000;
+SDRAM[3].EmcSelDpdCtrl = 0x00040008;
+SDRAM[3].EmcFdpdCtrlDq = 0x8020221f;
+SDRAM[3].EmcFdpdCtrlCmd = 0x0220f40f;
+SDRAM[3].EmcPmacroIbVrefDq_0 = 0x28282828;
+SDRAM[3].EmcPmacroIbVrefDq_1 = 0x28282828;
+SDRAM[3].EmcPmacroIbVrefDqs_0 = 0x11111111;
+SDRAM[3].EmcPmacroIbVrefDqs_1 = 0x11111111;
+SDRAM[3].EmcPmacroIbRxrt = 0x000000be;
+SDRAM[3].EmcCfgPipe1 = 0x0fff0fff;
+SDRAM[3].EmcCfgPipe2 = 0x0fff0fff;
+SDRAM[3].EmcPmacroQuseDdllRank0_0 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank0_1 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank0_2 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank0_3 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank0_4 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank0_5 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank1_0 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank1_1 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank1_2 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank1_3 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank1_4 = 0x00000000;
+SDRAM[3].EmcPmacroQuseDdllRank1_5 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank0_0 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank0_1 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank0_2 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank0_3 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank0_4 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank0_5 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank1_0 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank1_1 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank1_2 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank1_3 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank1_4 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqRank1_5 = 0x00000000;
+SDRAM[3].EmcPmacroObDdllLongDqsRank0_0 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank0_1 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank0_2 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank0_3 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank0_4 = 0x00090009;
+SDRAM[3].EmcPmacroObDdllLongDqsRank0_5 = 0x00090009;
+SDRAM[3].EmcPmacroObDdllLongDqsRank1_0 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank1_1 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank1_2 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank1_3 = 0x00320032;
+SDRAM[3].EmcPmacroObDdllLongDqsRank1_4 = 0x00090009;
+SDRAM[3].EmcPmacroObDdllLongDqsRank1_5 = 0x00090009;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank0_0 = 0x00280028;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank0_1 = 0x00280028;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank0_2 = 0x00280028;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank0_3 = 0x00280028;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank1_0 = 0x00280028;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank1_1 = 0x00280028;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank1_2 = 0x00280028;
+SDRAM[3].EmcPmacroIbDdllLongDqsRank1_3 = 0x00280028;
+SDRAM[3].EmcPmacroDdllLongCmd_0 = 0x00000000;
+SDRAM[3].EmcPmacroDdllLongCmd_1 = 0x00000000;
+SDRAM[3].EmcPmacroDdllLongCmd_2 = 0x00000000;
+SDRAM[3].EmcPmacroDdllLongCmd_3 = 0x00000000;
+SDRAM[3].EmcPmacroDdllLongCmd_4 = 0x00000000;
+SDRAM[3].EmcPmacroDdllShortCmd_0 = 0x00000000;
+SDRAM[3].EmcPmacroDdllShortCmd_1 = 0x00000000;
+SDRAM[3].EmcPmacroDdllShortCmd_2 = 0x00000000;
+SDRAM[3].WarmBootWait = 0x00000001;
+SDRAM[3].EmcOdtWrite = 0x00000000;
+SDRAM[3].EmcZcalInterval = 0x00064000;
+SDRAM[3].EmcZcalWaitCnt = 0x000900cc;
+SDRAM[3].EmcZcalMrwCmd = 0x0051004f;
+SDRAM[3].EmcMrsResetDll = 0x00000000;
+SDRAM[3].EmcZcalInitDev0 = 0x80000001;
+SDRAM[3].EmcZcalInitDev1 = 0x40000001;
+SDRAM[3].EmcZcalInitWait = 0x00000001;
+SDRAM[3].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[3].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[3].EmcZqCalDdr3WarmBoot = 0x00000011;
+SDRAM[3].EmcZqCalLpDdr4WarmBoot = 0x00000001;
+SDRAM[3].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[3].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[3].EmcMrsResetDllWait = 0x00000000;
+SDRAM[3].EmcMrsExtra = 0x00000000;
+SDRAM[3].EmcWarmBootMrsExtra = 0x00000000;
+SDRAM[3].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[3].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[3].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[3].EmcDdr2Wait = 0x00000000;
+SDRAM[3].EmcClkenOverride = 0x00000000;
+SDRAM[3].EmcExtraRefreshNum = 0x00000002;
+SDRAM[3].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[3].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[3].PmcVddpSel = 0x00000001;
+SDRAM[3].PmcVddpSelWait = 0x00000002;
+SDRAM[3].PmcDdrPwr = 0x0000000f;
+SDRAM[3].PmcDdrCfg = 0x20220100;
+SDRAM[3].PmcIoDpd3Req = 0x4bafffff;
+SDRAM[3].PmcIoDpd3ReqWait = 0x00000001;
+SDRAM[3].PmcIoDpd4ReqWait = 0x00000002;
+SDRAM[3].PmcRegShort = 0x00000000;
+SDRAM[3].PmcNoIoPower = 0x00000000;
+SDRAM[3].PmcDdrCntrlWait = 0x00000000;
+SDRAM[3].PmcDdrCntrl = 0x0007ff8b;
+SDRAM[3].EmcAcpdControl = 0x00000000;
+SDRAM[3].EmcSwizzleRank0Byte0 = 0x76342501;
+SDRAM[3].EmcSwizzleRank0Byte1 = 0x56243701;
+SDRAM[3].EmcSwizzleRank0Byte2 = 0x34267510;
+SDRAM[3].EmcSwizzleRank0Byte3 = 0x45763210;
+SDRAM[3].EmcSwizzleRank1Byte0 = 0x72345601;
+SDRAM[3].EmcSwizzleRank1Byte1 = 0x23456701;
+SDRAM[3].EmcSwizzleRank1Byte2 = 0x65427310;
+SDRAM[3].EmcSwizzleRank1Byte3 = 0x75432610;
+SDRAM[3].EmcTxdsrvttgen = 0x00000000;
+SDRAM[3].EmcDataBrlshft0 = 0x00249249;
+SDRAM[3].EmcDataBrlshft1 = 0x00249249;
+SDRAM[3].EmcDqsBrlshft0 = 0x00000000;
+SDRAM[3].EmcDqsBrlshft1 = 0x00000000;
+SDRAM[3].EmcCmdBrlshft0 = 0x00000000;
+SDRAM[3].EmcCmdBrlshft1 = 0x00000000;
+SDRAM[3].EmcCmdBrlshft2 = 0x00000012;
+SDRAM[3].EmcCmdBrlshft3 = 0x00000012;
+SDRAM[3].EmcQuseBrlshft0 = 0x00000000;
+SDRAM[3].EmcQuseBrlshft1 = 0x00000000;
+SDRAM[3].EmcQuseBrlshft2 = 0x00000000;
+SDRAM[3].EmcQuseBrlshft3 = 0x00000000;
+SDRAM[3].EmcDllCfg0 = 0x1f13412f;
+SDRAM[3].EmcDllCfg1 = 0x00010014;
+SDRAM[3].EmcPmcScratch1 = 0x4bafffff;
+SDRAM[3].EmcPmcScratch2 = 0x7fffffff;
+SDRAM[3].EmcPmcScratch3 = 0x4005d70b;
+SDRAM[3].EmcPmacroPadCfgCtrl = 0x00020000;
+SDRAM[3].EmcPmacroVttgenCtrl0 = 0x00030808;
+SDRAM[3].EmcPmacroVttgenCtrl1 = 0x00015000;
+SDRAM[3].EmcPmacroVttgenCtrl2 = 0x00101010;
+SDRAM[3].EmcPmacroBrickCtrlRfu1 = 0x00001600;
+SDRAM[3].EmcPmacroCmdBrickCtrlFdpd = 0x00000000;
+SDRAM[3].EmcPmacroBrickCtrlRfu2 = 0x00000000;
+SDRAM[3].EmcPmacroDataBrickCtrlFdpd = 0x00000000;
+SDRAM[3].EmcPmacroBgBiasCtrl0 = 0x00000030;
+SDRAM[3].EmcPmacroDataPadRxCtrl = 0x10050037;
+SDRAM[3].EmcPmacroCmdPadRxCtrl = 0x00000000;
+SDRAM[3].EmcPmacroDataRxTermMode = 0x00000010;
+SDRAM[3].EmcPmacroCmdRxTermMode = 0x00003000;
+SDRAM[3].EmcPmacroDataPadTxCtrl = 0x02000111;
+SDRAM[3].EmcPmacroCommonPadTxCtrl = 0x00000008;
+SDRAM[3].EmcPmacroCmdPadTxCtrl = 0x0a000000;
+SDRAM[3].EmcCfg3 = 0x00000040;
+SDRAM[3].EmcPmacroTxPwrd0 = 0x10000000;
+SDRAM[3].EmcPmacroTxPwrd1 = 0x08000000;
+SDRAM[3].EmcPmacroTxPwrd2 = 0x08000000;
+SDRAM[3].EmcPmacroTxPwrd3 = 0x08000000;
+SDRAM[3].EmcPmacroTxPwrd4 = 0x00000000;
+SDRAM[3].EmcPmacroTxPwrd5 = 0x00000000;
+SDRAM[3].EmcConfigSampleDelay = 0x00000020;
+SDRAM[3].EmcPmacroBrickMapping0 = 0x28190081;
+SDRAM[3].EmcPmacroBrickMapping1 = 0x44a53293;
+SDRAM[3].EmcPmacroBrickMapping2 = 0x76b76a5b;
+SDRAM[3].EmcPmacroTxSelClkSrc0 = 0x00000000;
+SDRAM[3].EmcPmacroTxSelClkSrc1 = 0x00000000;
+SDRAM[3].EmcPmacroTxSelClkSrc2 = 0x00000000;
+SDRAM[3].EmcPmacroTxSelClkSrc3 = 0x00000000;
+SDRAM[3].EmcPmacroTxSelClkSrc4 = 0x00000000;
+SDRAM[3].EmcPmacroTxSelClkSrc5 = 0x00000000;
+SDRAM[3].EmcPmacroDdllBypass = 0xefffefff;
+SDRAM[3].EmcPmacroDdllPwrd0 = 0xc0c0c0c0;
+SDRAM[3].EmcPmacroDdllPwrd1 = 0xc0c0c0c0;
+SDRAM[3].EmcPmacroDdllPwrd2 = 0xdcdcdcdc;
+SDRAM[3].EmcPmacroCmdCtrl0 = 0x0a0a0a0a;
+SDRAM[3].EmcPmacroCmdCtrl1 = 0x0a0a0a0a;
+SDRAM[3].EmcPmacroCmdCtrl2 = 0x0a0a0a0a;
+SDRAM[3].McEmemAdrCfg = 0x00000001;
+SDRAM[3].McEmemAdrCfgDev0 = 0x00070302;
+SDRAM[3].McEmemAdrCfgDev1 = 0x00070302;
+SDRAM[3].McEmemAdrCfgChannelMask = 0xffff2400;
+SDRAM[3].McEmemAdrCfgBankMask0 = 0x6e574400;
+SDRAM[3].McEmemAdrCfgBankMask1 = 0x39722800;
+SDRAM[3].McEmemAdrCfgBankMask2 = 0x4b9c1000;
+SDRAM[3].McEmemCfg = 0x00001000;
+SDRAM[3].McEmemArbCfg = 0x08000001;
+SDRAM[3].McEmemArbOutstandingReq = 0x8000004c;
+SDRAM[3].McEmemArbRefpbHpCtrl = 0x000a1020;
+SDRAM[3].McEmemArbRefpbBankCtrl = 0x80001028;
+SDRAM[3].McEmemArbTimingRcd = 0x00000001;
+SDRAM[3].McEmemArbTimingRp = 0x00000000;
+SDRAM[3].McEmemArbTimingRc = 0x00000003;
+SDRAM[3].McEmemArbTimingRas = 0x00000001;
+SDRAM[3].McEmemArbTimingFaw = 0x00000002;
+SDRAM[3].McEmemArbTimingRrd = 0x00000001;
+SDRAM[3].McEmemArbTimingRap2Pre = 0x00000002;
+SDRAM[3].McEmemArbTimingWap2Pre = 0x00000005;
+SDRAM[3].McEmemArbTimingR2R = 0x00000001;
+SDRAM[3].McEmemArbTimingW2W = 0x00000001;
+SDRAM[3].McEmemArbTimingR2W = 0x00000004;
+SDRAM[3].McEmemArbTimingW2R = 0x00000005;
+SDRAM[3].McEmemArbTimingRFCPB = 0x00000004;
+SDRAM[3].McEmemArbDaTurns = 0x02020000;
+SDRAM[3].McEmemArbDaCovers = 0x00030201;
+SDRAM[3].McEmemArbMisc0 = 0x71c30504;
+SDRAM[3].McEmemArbMisc1 = 0x70000f0f;
+SDRAM[3].McEmemArbMisc2 = 0x00000000;
+SDRAM[3].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[3].McEmemArbOverride = 0x10000000;
+SDRAM[3].McEmemArbOverride1 = 0x00000000;
+SDRAM[3].McEmemArbRsv = 0xff00ff00;
+SDRAM[3].McDaCfg0 = 0x00000001;
+SDRAM[3].McEmemArbTimingCcdmw = 0x00000008;
+SDRAM[3].McClkenOverride = 0x00008000;
+SDRAM[3].McStatControl = 0x00000000;
+SDRAM[3].McVideoProtectBom = 0xfff00000;
+SDRAM[3].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[3].McVideoProtectSizeMb = 0x00000000;
+SDRAM[3].McVideoProtectVprOverride = 0xe4bac343;
+SDRAM[3].McVideoProtectVprOverride1 = 0x00001ed3;
+SDRAM[3].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[3].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[3].McSecCarveoutBom = 0xfff00000;
+SDRAM[3].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[3].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[3].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[3].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1Bom = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1BomHi = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1Size128kb = 0x00000008;
+SDRAM[3].McGeneralizedCarveout1Access0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1Access1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1Access2 = 0x00300000;
+SDRAM[3].McGeneralizedCarveout1Access3 = 0x03000000;
+SDRAM[3].McGeneralizedCarveout1Access4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1ForceInternalAccess0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1ForceInternalAccess1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1ForceInternalAccess2 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1ForceInternalAccess3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1ForceInternalAccess4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout1Cfg0 = 0x04000c75;
+SDRAM[3].McGeneralizedCarveout2Bom = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2BomHi = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2Size128kb = 0x00000002;
+SDRAM[3].McGeneralizedCarveout2Access0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2Access1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2Access2 = 0x03000000;
+SDRAM[3].McGeneralizedCarveout2Access3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2Access4 = 0x00000300;
+SDRAM[3].McGeneralizedCarveout2ForceInternalAccess0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2ForceInternalAccess1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2ForceInternalAccess2 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2ForceInternalAccess3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2ForceInternalAccess4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout2Cfg0 = 0x0440167c;
+SDRAM[3].McGeneralizedCarveout3Bom = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3BomHi = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3Size128kb = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3Access0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3Access1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3Access2 = 0x03000000;
+SDRAM[3].McGeneralizedCarveout3Access3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3Access4 = 0x00000300;
+SDRAM[3].McGeneralizedCarveout3ForceInternalAccess0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3ForceInternalAccess1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3ForceInternalAccess2 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3ForceInternalAccess3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3ForceInternalAccess4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout3Cfg0 = 0x04401e7c;
+SDRAM[3].McGeneralizedCarveout4Bom = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4BomHi = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4Size128kb = 0x00000008;
+SDRAM[3].McGeneralizedCarveout4Access0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4Access1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4Access2 = 0x00300000;
+SDRAM[3].McGeneralizedCarveout4Access3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4Access4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4ForceInternalAccess0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4ForceInternalAccess1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout4Cfg0 = 0x04002442;
+SDRAM[3].McGeneralizedCarveout5Bom = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5BomHi = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5Size128kb = 0x00000008;
+SDRAM[3].McGeneralizedCarveout5Access0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5Access1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5Access2 = 0x00300000;
+SDRAM[3].McGeneralizedCarveout5Access3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5Access4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5ForceInternalAccess0 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5ForceInternalAccess1 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000;
+SDRAM[3].McGeneralizedCarveout5Cfg0 = 0x04002c42;
+SDRAM[3].EmcCaTrainingEnable = 0x00000000;
+SDRAM[3].SwizzleRankByteEncode = 0x0000002e;
+SDRAM[3].BootRomPatchControl = 0x00000000;
+SDRAM[3].BootRomPatchData = 0x00000000;
+SDRAM[3].McMtsCarveoutBom = 0xfff00000;
+SDRAM[3].McMtsCarveoutAdrHi = 0x00000000;
+SDRAM[3].McMtsCarveoutSizeMb = 0x00000000;
+SDRAM[3].McMtsCarveoutRegCtrl = 0x00000000;
diff --git a/src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc b/src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc
new file mode 100644
index 0000000000..745bb51810
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/sdram-samsung-3GB-204.inc
@@ -0,0 +1,476 @@
+{ /* generated from T210_A44_R1_LP4_DSC_204Mhz.cfg; do not edit. */
+ .MemoryType = NvBootMemoryType_LpDdr4,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x00000022,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMPostDivider = 0x00000000,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x7001bc3c,
+ .EmcBctSpare5 = 0x00000032,
+ .EmcBctSpare6 = 0x7001b404,
+ .EmcBctSpare7 = 0x76342501,
+ .EmcBctSpare8 = 0x7000e6c8,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcBctSpare12 = 0x7001bc3c,
+ .EmcBctSpare13 = 0x00000033,
+ .EmcClockSource = 0x40188002,
+ .EmcClockSourceDll = 0x40000000,
+ .ClkRstControllerPllmMisc2Override = 0x00000000,
+ .ClkRstControllerPllmMisc2OverrideEnable = 0x00000000,
+ .ClearClk2Mc1 = 0x00000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa01a51d8,
+ .EmcAutoCalConfig2 = 0x05500000,
+ .EmcAutoCalConfig3 = 0x00770000,
+ .EmcAutoCalConfig4 = 0x00770000,
+ .EmcAutoCalConfig5 = 0x00770000,
+ .EmcAutoCalConfig6 = 0x00770000,
+ .EmcAutoCalConfig7 = 0x00770000,
+ .EmcAutoCalConfig8 = 0x00770000,
+ .EmcAutoCalVrefSel0 = 0xb3afa6a6,
+ .EmcAutoCalVrefSel1 = 0x00009e3c,
+ .EmcAutoCalChannel = 0xc1e00303,
+ .EmcPmacroAutocalCfg0 = 0x04040404,
+ .EmcPmacroAutocalCfg1 = 0x04040404,
+ .EmcPmacroAutocalCfg2 = 0x00000000,
+ .EmcPmacroRxTerm = 0x1f1f1f1f,
+ .EmcPmacroDqTxDrv = 0x1f1f1f1f,
+ .EmcPmacroCaTxDrv = 0x1f1f1f1f,
+ .EmcPmacroCmdTxDrv = 0x00001f1f,
+ .EmcPmacroAutocalCfgCommon = 0x00000804,
+ .EmcPmacroZctrl = 0x00000550,
+ .EmcAutoCalWait = 0x000001a1,
+ .EmcXm2CompPadCtrl = 0x00000032,
+ .EmcXm2CompPadCtrl2 = 0x00000000,
+ .EmcXm2CompPadCtrl3 = 0x00000000,
+ .EmcAdrCfg = 0x00000001,
+ .EmcPinProgramWait = 0x00000002,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcPinGpioEn = 0x00000003,
+ .EmcPinGpio = 0x00000003,
+ .EmcTimingControlWait = 0x0000001e,
+ .EmcRc = 0x0000000d,
+ .EmcRfc = 0x00000025,
+ .EmcRfcPb = 0x00000013,
+ .EmcRefctrl2 = 0x00000000,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x00000009,
+ .EmcRp = 0x00000004,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x0000000b,
+ .EmcW2r = 0x0000000d,
+ .EmcR2p = 0x00000008,
+ .EmcW2p = 0x0000000b,
+ .EmcTppd = 0x00000004,
+ .EmcCcdmw = 0x00000020,
+ .EmcRdRcd = 0x00000006,
+ .EmcWrRcd = 0x00000006,
+ .EmcRrd = 0x00000006,
+ .EmcRext = 0x00000003,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000004,
+ .EmcWdvChk = 0x00000006,
+ .EmcWsv = 0x00000002,
+ .EmcWev = 0x00000000,
+ .EmcWdvMask = 0x00000004,
+ .EmcWsDuration = 0x00000008,
+ .EmcWeDuration = 0x0000000d,
+ .EmcQUse = 0x00000005,
+ .EmcQuseWidth = 0x00000006,
+ .EmcIbdly = 0x00000000,
+ .EmcObdly = 0x00000000,
+ .EmcEInput = 0x00000002,
+ .EmcEInputDuration = 0x0000000d,
+ .EmcPutermExtra = 0x00000002,
+ .EmcPutermWidth = 0x0000000b,
+ .EmcQRst = 0x00010000,
+ .EmcQSafe = 0x00000012,
+ .EmcRdv = 0x00000014,
+ .EmcRdvMask = 0x00000016,
+ .EmcRdvEarly = 0x00000012,
+ .EmcRdvEarlyMask = 0x00000014,
+ .EmcQpop = 0x0000000a,
+ .EmcRefresh = 0x00000304,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000000c1,
+ .EmcPdEx2Wr = 0x00000008,
+ .EmcPdEx2Rd = 0x00000008,
+ .EmcPChg2Pden = 0x00000003,
+ .EmcAct2Pden = 0x00000003,
+ .EmcAr2Pden = 0x00000003,
+ .EmcRw2Pden = 0x00000012,
+ .EmcCke2Pden = 0x00000005,
+ .EmcPdex2Cke = 0x00000002,
+ .EmcPdex2Mrr = 0x0000000d,
+ .EmcTxsr = 0x00000027,
+ .EmcTxsrDll = 0x00000027,
+ .EmcTcke = 0x00000005,
+ .EmcTckesr = 0x00000005,
+ .EmcTpd = 0x00000004,
+ .EmcTfaw = 0x00000009,
+ .EmcTrpab = 0x00000005,
+ .EmcTClkStable = 0x00000003,
+ .EmcTClkStop = 0x00000009,
+ .EmcTRefBw = 0x0000031c,
+ .EmcFbioCfg5 = 0x9160a00d,
+ .EmcFbioCfg7 = 0x00003bbf,
+ .EmcFbioCfg8 = 0x0cf30000,
+ .EmcCmdMappingCmd0_0 = 0x07050203,
+ .EmcCmdMappingCmd0_1 = 0x06041b1c,
+ .EmcCmdMappingCmd0_2 = 0x05252523,
+ .EmcCmdMappingCmd1_0 = 0x1e0d0b0a,
+ .EmcCmdMappingCmd1_1 = 0x240c091d,
+ .EmcCmdMappingCmd1_2 = 0x04262608,
+ .EmcCmdMappingCmd2_0 = 0x051b0302,
+ .EmcCmdMappingCmd2_1 = 0x0604231c,
+ .EmcCmdMappingCmd2_2 = 0x09252507,
+ .EmcCmdMappingCmd3_0 = 0x0c0b0d0a,
+ .EmcCmdMappingCmd3_1 = 0x08091e1d,
+ .EmcCmdMappingCmd3_2 = 0x08262624,
+ .EmcCmdMappingByte = 0x0a070623,
+ .EmcFbioSpare = 0x00000012,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x00000000,
+ .EmcEmrs = 0x00000000,
+ .EmcEmrs2 = 0x00000000,
+ .EmcEmrs3 = 0x00000000,
+ .EmcMrw1 = 0x08010004,
+ .EmcMrw2 = 0x08020000,
+ .EmcMrw3 = 0x080d0000,
+ .EmcMrw4 = 0xc0000000,
+ .EmcMrw6 = 0x08037171,
+ .EmcMrw8 = 0x080b0000,
+ .EmcMrw9 = 0x0c0e6b6b,
+ .EmcMrw10 = 0x00000000,
+ .EmcMrw12 = 0x0c0d0808,
+ .EmcMrw13 = 0x0c0d0000,
+ .EmcMrw14 = 0x08161414,
+ .EmcMrwExtra = 0x08010004,
+ .EmcWarmBootMrwExtra = 0x08110000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000001,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x00cc0015,
+ .EmcMrsWaitCnt2 = 0x0033000a,
+ .EmcCfg = 0xf3200000,
+ .EmcCfg2 = 0x00110805,
+ .EmcCfgPipe = 0x0fff0fff,
+ .EmcCfgPipeClk = 0x00000000,
+ .EmcFdpdCtrlCmdNoRamp = 0x00000001,
+ .EmcCfgUpdate = 0x70000301,
+ .EmcDbg = 0x01000c00,
+ .EmcDbgWriteMux = 0x00000001,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x80000713,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0x002c00a0,
+ .EmcCfgDigDll_1 = 0x00003701,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000000,
+ .EmcSelDpdCtrl = 0x00040008,
+ .EmcFdpdCtrlDq = 0x8020221f,
+ .EmcFdpdCtrlCmd = 0x0220f40f,
+ .EmcPmacroIbVrefDq_0 = 0x28282828,
+ .EmcPmacroIbVrefDq_1 = 0x28282828,
+ .EmcPmacroIbVrefDqs_0 = 0x11111111,
+ .EmcPmacroIbVrefDqs_1 = 0x11111111,
+ .EmcPmacroIbRxrt = 0x000000be,
+ .EmcCfgPipe1 = 0x0fff0fff,
+ .EmcCfgPipe2 = 0x0fff0fff,
+ .EmcPmacroQuseDdllRank0_0 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_1 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_2 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_3 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_4 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_5 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_0 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_1 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_2 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_3 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_4 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_5 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_0 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_1 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_2 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_3 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_4 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_5 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_0 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_1 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_2 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_3 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_4 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_5 = 0x00000000,
+ .EmcPmacroObDdllLongDqsRank0_0 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_1 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_2 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_3 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_4 = 0x00090009,
+ .EmcPmacroObDdllLongDqsRank0_5 = 0x00090009,
+ .EmcPmacroObDdllLongDqsRank1_0 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_1 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_2 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_3 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_4 = 0x00090009,
+ .EmcPmacroObDdllLongDqsRank1_5 = 0x00090009,
+ .EmcPmacroIbDdllLongDqsRank0_0 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank0_1 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank0_2 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank0_3 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_0 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_1 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_2 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_3 = 0x00280028,
+ .EmcPmacroDdllLongCmd_0 = 0x00000000,
+ .EmcPmacroDdllLongCmd_1 = 0x00000000,
+ .EmcPmacroDdllLongCmd_2 = 0x00000000,
+ .EmcPmacroDdllLongCmd_3 = 0x00000000,
+ .EmcPmacroDdllLongCmd_4 = 0x00000000,
+ .EmcPmacroDdllShortCmd_0 = 0x00000000,
+ .EmcPmacroDdllShortCmd_1 = 0x00000000,
+ .EmcPmacroDdllShortCmd_2 = 0x00000000,
+ .WarmBootWait = 0x00000001,
+ .EmcOdtWrite = 0x00000000,
+ .EmcZcalInterval = 0x00064000,
+ .EmcZcalWaitCnt = 0x000900cc,
+ .EmcZcalMrwCmd = 0x0051004f,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000001,
+ .EmcZcalInitDev1 = 0x40000001,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000011,
+ .EmcZqCalLpDdr4WarmBoot = 0x00000001,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x00000000,
+ .EmcWarmBootMrsExtra = 0x00000000,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000001,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x0000000f,
+ .PmcDdrCfg = 0x20220100,
+ .PmcIoDpd3Req = 0x4bafffff,
+ .PmcIoDpd3ReqWait = 0x00000001,
+ .PmcIoDpd4ReqWait = 0x00000002,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcDdrCntrlWait = 0x00000000,
+ .PmcDdrCntrl = 0x0007ff8b,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0Byte0 = 0x76342501,
+ .EmcSwizzleRank0Byte1 = 0x56243701,
+ .EmcSwizzleRank0Byte2 = 0x34267510,
+ .EmcSwizzleRank0Byte3 = 0x45763210,
+ .EmcSwizzleRank1Byte0 = 0x72345601,
+ .EmcSwizzleRank1Byte1 = 0x23456701,
+ .EmcSwizzleRank1Byte2 = 0x65427310,
+ .EmcSwizzleRank1Byte3 = 0x75432610,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcDataBrlshft0 = 0x00249249,
+ .EmcDataBrlshft1 = 0x00249249,
+ .EmcDqsBrlshft0 = 0x00000000,
+ .EmcDqsBrlshft1 = 0x00000000,
+ .EmcCmdBrlshft0 = 0x00000000,
+ .EmcCmdBrlshft1 = 0x00000000,
+ .EmcCmdBrlshft2 = 0x00000012,
+ .EmcCmdBrlshft3 = 0x00000012,
+ .EmcQuseBrlshft0 = 0x00000000,
+ .EmcQuseBrlshft1 = 0x00000000,
+ .EmcQuseBrlshft2 = 0x00000000,
+ .EmcQuseBrlshft3 = 0x00000000,
+ .EmcDllCfg0 = 0x1f13412f,
+ .EmcDllCfg1 = 0x00010014,
+ .EmcPmcScratch1 = 0x4bafffff,
+ .EmcPmcScratch2 = 0x7fffffff,
+ .EmcPmcScratch3 = 0x4005d70b,
+ .EmcPmacroPadCfgCtrl = 0x00020000,
+ .EmcPmacroVttgenCtrl0 = 0x00030808,
+ .EmcPmacroVttgenCtrl1 = 0x00015000,
+ .EmcPmacroVttgenCtrl2 = 0x00101010,
+ .EmcPmacroBrickCtrlRfu1 = 0x00001600,
+ .EmcPmacroCmdBrickCtrlFdpd = 0x00000000,
+ .EmcPmacroBrickCtrlRfu2 = 0x00000000,
+ .EmcPmacroDataBrickCtrlFdpd = 0x00000000,
+ .EmcPmacroBgBiasCtrl0 = 0x00000030,
+ .EmcPmacroDataPadRxCtrl = 0x10050037,
+ .EmcPmacroCmdPadRxCtrl = 0x00000000,
+ .EmcPmacroDataRxTermMode = 0x00000010,
+ .EmcPmacroCmdRxTermMode = 0x00003000,
+ .EmcPmacroDataPadTxCtrl = 0x02000111,
+ .EmcPmacroCommonPadTxCtrl = 0x00000008,
+ .EmcPmacroCmdPadTxCtrl = 0x0a000000,
+ .EmcCfg3 = 0x00000040,
+ .EmcPmacroTxPwrd0 = 0x10000000,
+ .EmcPmacroTxPwrd1 = 0x08000000,
+ .EmcPmacroTxPwrd2 = 0x08000000,
+ .EmcPmacroTxPwrd3 = 0x08000000,
+ .EmcPmacroTxPwrd4 = 0x00000000,
+ .EmcPmacroTxPwrd5 = 0x00000000,
+ .EmcConfigSampleDelay = 0x00000020,
+ .EmcPmacroBrickMapping0 = 0x28190081,
+ .EmcPmacroBrickMapping1 = 0x44a53293,
+ .EmcPmacroBrickMapping2 = 0x76b76a5b,
+ .EmcPmacroTxSelClkSrc0 = 0x00000000,
+ .EmcPmacroTxSelClkSrc1 = 0x00000000,
+ .EmcPmacroTxSelClkSrc2 = 0x00000000,
+ .EmcPmacroTxSelClkSrc3 = 0x00000000,
+ .EmcPmacroTxSelClkSrc4 = 0x00000000,
+ .EmcPmacroTxSelClkSrc5 = 0x00000000,
+ .EmcPmacroDdllBypass = 0xefffefff,
+ .EmcPmacroDdllPwrd0 = 0xc0c0c0c0,
+ .EmcPmacroDdllPwrd1 = 0xc0c0c0c0,
+ .EmcPmacroDdllPwrd2 = 0xdcdcdcdc,
+ .EmcPmacroCmdCtrl0 = 0x0a0a0a0a,
+ .EmcPmacroCmdCtrl1 = 0x0a0a0a0a,
+ .EmcPmacroCmdCtrl2 = 0x0a0a0a0a,
+ .McEmemAdrCfg = 0x00000001,
+ .McEmemAdrCfgDev0 = 0x000d0302,
+ .McEmemAdrCfgDev1 = 0x000d0302,
+ .McEmemAdrCfgChannelMask = 0xffff2400,
+ .McEmemAdrCfgBankMask0 = 0x6e574400,
+ .McEmemAdrCfgBankMask1 = 0x39722800,
+ .McEmemAdrCfgBankMask2 = 0x4b9c1000,
+ .McEmemCfg = 0x00000c00,
+ .McEmemArbCfg = 0x08000001,
+ .McEmemArbOutstandingReq = 0x8000004c,
+ .McEmemArbRefpbHpCtrl = 0x000a1020,
+ .McEmemArbRefpbBankCtrl = 0x80001028,
+ .McEmemArbTimingRcd = 0x00000001,
+ .McEmemArbTimingRp = 0x00000000,
+ .McEmemArbTimingRc = 0x00000003,
+ .McEmemArbTimingRas = 0x00000001,
+ .McEmemArbTimingFaw = 0x00000002,
+ .McEmemArbTimingRrd = 0x00000001,
+ .McEmemArbTimingRap2Pre = 0x00000002,
+ .McEmemArbTimingWap2Pre = 0x00000005,
+ .McEmemArbTimingR2R = 0x00000001,
+ .McEmemArbTimingW2W = 0x00000001,
+ .McEmemArbTimingR2W = 0x00000004,
+ .McEmemArbTimingW2R = 0x00000005,
+ .McEmemArbTimingRFCPB = 0x00000004,
+ .McEmemArbDaTurns = 0x02020000,
+ .McEmemArbDaCovers = 0x00030201,
+ .McEmemArbMisc0 = 0x71c30504,
+ .McEmemArbMisc1 = 0x70000f0f,
+ .McEmemArbMisc2 = 0x00000000,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McDaCfg0 = 0x00000001,
+ .McEmemArbTimingCcdmw = 0x00000008,
+ .McClkenOverride = 0x00008000,
+ .McStatControl = 0x00000000,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac343,
+ .McVideoProtectVprOverride1 = 0x00001ed3,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .McGeneralizedCarveout1Bom = 0x00000000,
+ .McGeneralizedCarveout1BomHi = 0x00000000,
+ .McGeneralizedCarveout1Size128kb = 0x00000008,
+ .McGeneralizedCarveout1Access0 = 0x00000000,
+ .McGeneralizedCarveout1Access1 = 0x00000000,
+ .McGeneralizedCarveout1Access2 = 0x00300000,
+ .McGeneralizedCarveout1Access3 = 0x03000000,
+ .McGeneralizedCarveout1Access4 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout1Cfg0 = 0x04000c75,
+ .McGeneralizedCarveout2Bom = 0x00000000,
+ .McGeneralizedCarveout2BomHi = 0x00000000,
+ .McGeneralizedCarveout2Size128kb = 0x00000002,
+ .McGeneralizedCarveout2Access0 = 0x00000000,
+ .McGeneralizedCarveout2Access1 = 0x00000000,
+ .McGeneralizedCarveout2Access2 = 0x03000000,
+ .McGeneralizedCarveout2Access3 = 0x00000000,
+ .McGeneralizedCarveout2Access4 = 0x00000300,
+ .McGeneralizedCarveout2ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout2Cfg0 = 0x0440167c,
+ .McGeneralizedCarveout3Bom = 0x00000000,
+ .McGeneralizedCarveout3BomHi = 0x00000000,
+ .McGeneralizedCarveout3Size128kb = 0x00000000,
+ .McGeneralizedCarveout3Access0 = 0x00000000,
+ .McGeneralizedCarveout3Access1 = 0x00000000,
+ .McGeneralizedCarveout3Access2 = 0x03000000,
+ .McGeneralizedCarveout3Access3 = 0x00000000,
+ .McGeneralizedCarveout3Access4 = 0x00000300,
+ .McGeneralizedCarveout3ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout3Cfg0 = 0x04401e7c,
+ .McGeneralizedCarveout4Bom = 0x00000000,
+ .McGeneralizedCarveout4BomHi = 0x00000000,
+ .McGeneralizedCarveout4Size128kb = 0x00000008,
+ .McGeneralizedCarveout4Access0 = 0x00000000,
+ .McGeneralizedCarveout4Access1 = 0x00000000,
+ .McGeneralizedCarveout4Access2 = 0x00300000,
+ .McGeneralizedCarveout4Access3 = 0x00000000,
+ .McGeneralizedCarveout4Access4 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout4Cfg0 = 0x04002442,
+ .McGeneralizedCarveout5Bom = 0x00000000,
+ .McGeneralizedCarveout5BomHi = 0x00000000,
+ .McGeneralizedCarveout5Size128kb = 0x00000008,
+ .McGeneralizedCarveout5Access0 = 0x00000000,
+ .McGeneralizedCarveout5Access1 = 0x00000000,
+ .McGeneralizedCarveout5Access2 = 0x00300000,
+ .McGeneralizedCarveout5Access3 = 0x00000000,
+ .McGeneralizedCarveout5Access4 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout5Cfg0 = 0x04002c42,
+ .EmcCaTrainingEnable = 0x00000000,
+ .SwizzleRankByteEncode = 0x0000002e,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0xfff00000,
+ .McMtsCarveoutAdrHi = 0x00000000,
+ .McMtsCarveoutSizeMb = 0x00000000,
+ .McMtsCarveoutRegCtrl = 0x00000000,
+},
diff --git a/src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc b/src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc
new file mode 100644
index 0000000000..2e7142e011
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/sdram-samsung-4GB-204.inc
@@ -0,0 +1,476 @@
+{ /* generated from T210_A44_R1_LP4_DSC_4G_204Mhz.cfg; do not edit. */
+ .MemoryType = NvBootMemoryType_LpDdr4,
+ .PllMInputDivider = 0x00000001,
+ .PllMFeedbackDivider = 0x00000022,
+ .PllMStableTime = 0x0000012c,
+ .PllMSetupControl = 0x00000000,
+ .PllMPostDivider = 0x00000000,
+ .PllMKCP = 0x00000000,
+ .PllMKVCO = 0x00000000,
+ .EmcBctSpare0 = 0x00000000,
+ .EmcBctSpare1 = 0x00000000,
+ .EmcBctSpare2 = 0x00000000,
+ .EmcBctSpare3 = 0x00000000,
+ .EmcBctSpare4 = 0x7001bc3c,
+ .EmcBctSpare5 = 0x00000032,
+ .EmcBctSpare6 = 0x7001b404,
+ .EmcBctSpare7 = 0x76342501,
+ .EmcBctSpare8 = 0x7000e6c8,
+ .EmcBctSpare9 = 0x00000000,
+ .EmcBctSpare10 = 0x00000000,
+ .EmcBctSpare11 = 0x00000000,
+ .EmcBctSpare12 = 0x7001bc3c,
+ .EmcBctSpare13 = 0x00000033,
+ .EmcClockSource = 0x40188002,
+ .EmcClockSourceDll = 0x40000000,
+ .ClkRstControllerPllmMisc2Override = 0x00000000,
+ .ClkRstControllerPllmMisc2OverrideEnable = 0x00000000,
+ .ClearClk2Mc1 = 0x00000000,
+ .EmcAutoCalInterval = 0x001fffff,
+ .EmcAutoCalConfig = 0xa01a51d8,
+ .EmcAutoCalConfig2 = 0x05500000,
+ .EmcAutoCalConfig3 = 0x00770000,
+ .EmcAutoCalConfig4 = 0x00770000,
+ .EmcAutoCalConfig5 = 0x00770000,
+ .EmcAutoCalConfig6 = 0x00770000,
+ .EmcAutoCalConfig7 = 0x00770000,
+ .EmcAutoCalConfig8 = 0x00770000,
+ .EmcAutoCalVrefSel0 = 0xb3afa6a6,
+ .EmcAutoCalVrefSel1 = 0x00009e3c,
+ .EmcAutoCalChannel = 0xc1e00303,
+ .EmcPmacroAutocalCfg0 = 0x04040404,
+ .EmcPmacroAutocalCfg1 = 0x04040404,
+ .EmcPmacroAutocalCfg2 = 0x00000000,
+ .EmcPmacroRxTerm = 0x1f1f1f1f,
+ .EmcPmacroDqTxDrv = 0x1f1f1f1f,
+ .EmcPmacroCaTxDrv = 0x1f1f1f1f,
+ .EmcPmacroCmdTxDrv = 0x00001f1f,
+ .EmcPmacroAutocalCfgCommon = 0x00000804,
+ .EmcPmacroZctrl = 0x00000550,
+ .EmcAutoCalWait = 0x000001a1,
+ .EmcXm2CompPadCtrl = 0x00000032,
+ .EmcXm2CompPadCtrl2 = 0x00000000,
+ .EmcXm2CompPadCtrl3 = 0x00000000,
+ .EmcAdrCfg = 0x00000001,
+ .EmcPinProgramWait = 0x00000002,
+ .EmcPinExtraWait = 0x00000000,
+ .EmcPinGpioEn = 0x00000003,
+ .EmcPinGpio = 0x00000003,
+ .EmcTimingControlWait = 0x0000001e,
+ .EmcRc = 0x0000000d,
+ .EmcRfc = 0x00000025,
+ .EmcRfcPb = 0x00000013,
+ .EmcRefctrl2 = 0x00000000,
+ .EmcRfcSlr = 0x00000000,
+ .EmcRas = 0x00000009,
+ .EmcRp = 0x00000004,
+ .EmcR2r = 0x00000000,
+ .EmcW2w = 0x00000000,
+ .EmcR2w = 0x0000000b,
+ .EmcW2r = 0x0000000d,
+ .EmcR2p = 0x00000008,
+ .EmcW2p = 0x0000000b,
+ .EmcTppd = 0x00000004,
+ .EmcCcdmw = 0x00000020,
+ .EmcRdRcd = 0x00000006,
+ .EmcWrRcd = 0x00000006,
+ .EmcRrd = 0x00000006,
+ .EmcRext = 0x00000003,
+ .EmcWext = 0x00000000,
+ .EmcWdv = 0x00000004,
+ .EmcWdvChk = 0x00000006,
+ .EmcWsv = 0x00000002,
+ .EmcWev = 0x00000000,
+ .EmcWdvMask = 0x00000004,
+ .EmcWsDuration = 0x00000008,
+ .EmcWeDuration = 0x0000000d,
+ .EmcQUse = 0x00000005,
+ .EmcQuseWidth = 0x00000006,
+ .EmcIbdly = 0x00000000,
+ .EmcObdly = 0x00000000,
+ .EmcEInput = 0x00000002,
+ .EmcEInputDuration = 0x0000000d,
+ .EmcPutermExtra = 0x00000002,
+ .EmcPutermWidth = 0x0000000b,
+ .EmcQRst = 0x00010000,
+ .EmcQSafe = 0x00000012,
+ .EmcRdv = 0x00000014,
+ .EmcRdvMask = 0x00000016,
+ .EmcRdvEarly = 0x00000012,
+ .EmcRdvEarlyMask = 0x00000014,
+ .EmcQpop = 0x0000000a,
+ .EmcRefresh = 0x00000304,
+ .EmcBurstRefreshNum = 0x00000000,
+ .EmcPreRefreshReqCnt = 0x000000c1,
+ .EmcPdEx2Wr = 0x00000008,
+ .EmcPdEx2Rd = 0x00000008,
+ .EmcPChg2Pden = 0x00000003,
+ .EmcAct2Pden = 0x00000003,
+ .EmcAr2Pden = 0x00000003,
+ .EmcRw2Pden = 0x00000012,
+ .EmcCke2Pden = 0x00000005,
+ .EmcPdex2Cke = 0x00000002,
+ .EmcPdex2Mrr = 0x0000000d,
+ .EmcTxsr = 0x00000027,
+ .EmcTxsrDll = 0x00000027,
+ .EmcTcke = 0x00000005,
+ .EmcTckesr = 0x00000005,
+ .EmcTpd = 0x00000004,
+ .EmcTfaw = 0x00000009,
+ .EmcTrpab = 0x00000005,
+ .EmcTClkStable = 0x00000003,
+ .EmcTClkStop = 0x00000009,
+ .EmcTRefBw = 0x0000031c,
+ .EmcFbioCfg5 = 0x9160a00d,
+ .EmcFbioCfg7 = 0x00003bbf,
+ .EmcFbioCfg8 = 0x0cf30000,
+ .EmcCmdMappingCmd0_0 = 0x07050203,
+ .EmcCmdMappingCmd0_1 = 0x06041b1c,
+ .EmcCmdMappingCmd0_2 = 0x05252523,
+ .EmcCmdMappingCmd1_0 = 0x1e0d0b0a,
+ .EmcCmdMappingCmd1_1 = 0x240c091d,
+ .EmcCmdMappingCmd1_2 = 0x04262608,
+ .EmcCmdMappingCmd2_0 = 0x051b0302,
+ .EmcCmdMappingCmd2_1 = 0x0604231c,
+ .EmcCmdMappingCmd2_2 = 0x09252507,
+ .EmcCmdMappingCmd3_0 = 0x0c0b0d0a,
+ .EmcCmdMappingCmd3_1 = 0x08091e1d,
+ .EmcCmdMappingCmd3_2 = 0x08262624,
+ .EmcCmdMappingByte = 0x0a070623,
+ .EmcFbioSpare = 0x00000012,
+ .EmcCfgRsv = 0xff00ff00,
+ .EmcMrs = 0x00000000,
+ .EmcEmrs = 0x00000000,
+ .EmcEmrs2 = 0x00000000,
+ .EmcEmrs3 = 0x00000000,
+ .EmcMrw1 = 0x08010004,
+ .EmcMrw2 = 0x08020000,
+ .EmcMrw3 = 0x080d0000,
+ .EmcMrw4 = 0xc0000000,
+ .EmcMrw6 = 0x08037171,
+ .EmcMrw8 = 0x080b0000,
+ .EmcMrw9 = 0x0c0e6b6b,
+ .EmcMrw10 = 0x00000000,
+ .EmcMrw12 = 0x0c0d0808,
+ .EmcMrw13 = 0x0c0d0000,
+ .EmcMrw14 = 0x08161414,
+ .EmcMrwExtra = 0x08010004,
+ .EmcWarmBootMrwExtra = 0x08110000,
+ .EmcWarmBootExtraModeRegWriteEnable = 0x00000001,
+ .EmcExtraModeRegWriteEnable = 0x00000000,
+ .EmcMrwResetCommand = 0x00000000,
+ .EmcMrwResetNInitWait = 0x00000000,
+ .EmcMrsWaitCnt = 0x00cc0015,
+ .EmcMrsWaitCnt2 = 0x0033000a,
+ .EmcCfg = 0xf3200000,
+ .EmcCfg2 = 0x00110805,
+ .EmcCfgPipe = 0x0fff0fff,
+ .EmcCfgPipeClk = 0x00000000,
+ .EmcFdpdCtrlCmdNoRamp = 0x00000001,
+ .EmcCfgUpdate = 0x70000301,
+ .EmcDbg = 0x01000c00,
+ .EmcDbgWriteMux = 0x00000001,
+ .EmcCmdQ = 0x10004408,
+ .EmcMc2EmcQ = 0x06000404,
+ .EmcDynSelfRefControl = 0x80000713,
+ .AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
+ .EmcCfgDigDll = 0x002c00a0,
+ .EmcCfgDigDll_1 = 0x00003701,
+ .EmcCfgDigDllPeriod = 0x00008000,
+ .EmcDevSelect = 0x00000000,
+ .EmcSelDpdCtrl = 0x00040008,
+ .EmcFdpdCtrlDq = 0x8020221f,
+ .EmcFdpdCtrlCmd = 0x0220f40f,
+ .EmcPmacroIbVrefDq_0 = 0x28282828,
+ .EmcPmacroIbVrefDq_1 = 0x28282828,
+ .EmcPmacroIbVrefDqs_0 = 0x11111111,
+ .EmcPmacroIbVrefDqs_1 = 0x11111111,
+ .EmcPmacroIbRxrt = 0x000000be,
+ .EmcCfgPipe1 = 0x0fff0fff,
+ .EmcCfgPipe2 = 0x0fff0fff,
+ .EmcPmacroQuseDdllRank0_0 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_1 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_2 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_3 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_4 = 0x00000000,
+ .EmcPmacroQuseDdllRank0_5 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_0 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_1 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_2 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_3 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_4 = 0x00000000,
+ .EmcPmacroQuseDdllRank1_5 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_0 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_1 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_2 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_3 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_4 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank0_5 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_0 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_1 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_2 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_3 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_4 = 0x00000000,
+ .EmcPmacroObDdllLongDqRank1_5 = 0x00000000,
+ .EmcPmacroObDdllLongDqsRank0_0 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_1 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_2 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_3 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank0_4 = 0x00090009,
+ .EmcPmacroObDdllLongDqsRank0_5 = 0x00090009,
+ .EmcPmacroObDdllLongDqsRank1_0 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_1 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_2 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_3 = 0x00320032,
+ .EmcPmacroObDdllLongDqsRank1_4 = 0x00090009,
+ .EmcPmacroObDdllLongDqsRank1_5 = 0x00090009,
+ .EmcPmacroIbDdllLongDqsRank0_0 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank0_1 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank0_2 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank0_3 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_0 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_1 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_2 = 0x00280028,
+ .EmcPmacroIbDdllLongDqsRank1_3 = 0x00280028,
+ .EmcPmacroDdllLongCmd_0 = 0x00000000,
+ .EmcPmacroDdllLongCmd_1 = 0x00000000,
+ .EmcPmacroDdllLongCmd_2 = 0x00000000,
+ .EmcPmacroDdllLongCmd_3 = 0x00000000,
+ .EmcPmacroDdllLongCmd_4 = 0x00000000,
+ .EmcPmacroDdllShortCmd_0 = 0x00000000,
+ .EmcPmacroDdllShortCmd_1 = 0x00000000,
+ .EmcPmacroDdllShortCmd_2 = 0x00000000,
+ .WarmBootWait = 0x00000001,
+ .EmcOdtWrite = 0x00000000,
+ .EmcZcalInterval = 0x00064000,
+ .EmcZcalWaitCnt = 0x000900cc,
+ .EmcZcalMrwCmd = 0x0051004f,
+ .EmcMrsResetDll = 0x00000000,
+ .EmcZcalInitDev0 = 0x80000001,
+ .EmcZcalInitDev1 = 0x40000001,
+ .EmcZcalInitWait = 0x00000001,
+ .EmcZcalWarmColdBootEnables = 0x00000003,
+ .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
+ .EmcZqCalDdr3WarmBoot = 0x00000011,
+ .EmcZqCalLpDdr4WarmBoot = 0x00000001,
+ .EmcZcalWarmBootWait = 0x00000001,
+ .EmcMrsWarmBootEnable = 0x00000001,
+ .EmcMrsResetDllWait = 0x00000000,
+ .EmcMrsExtra = 0x00000000,
+ .EmcWarmBootMrsExtra = 0x00000000,
+ .EmcEmrsDdr2DllEnable = 0x00000000,
+ .EmcMrsDdr2DllReset = 0x00000000,
+ .EmcEmrsDdr2OcdCalib = 0x00000000,
+ .EmcDdr2Wait = 0x00000000,
+ .EmcClkenOverride = 0x00000000,
+ .EmcExtraRefreshNum = 0x00000002,
+ .EmcClkenOverrideAllWarmBoot = 0x00000000,
+ .McClkenOverrideAllWarmBoot = 0x00000000,
+ .EmcCfgDigDllPeriodWarmBoot = 0x00000003,
+ .PmcVddpSel = 0x00000001,
+ .PmcVddpSelWait = 0x00000002,
+ .PmcDdrPwr = 0x0000000f,
+ .PmcDdrCfg = 0x20220100,
+ .PmcIoDpd3Req = 0x4bafffff,
+ .PmcIoDpd3ReqWait = 0x00000001,
+ .PmcIoDpd4ReqWait = 0x00000002,
+ .PmcRegShort = 0x00000000,
+ .PmcNoIoPower = 0x00000000,
+ .PmcDdrCntrlWait = 0x00000000,
+ .PmcDdrCntrl = 0x0007ff8b,
+ .EmcAcpdControl = 0x00000000,
+ .EmcSwizzleRank0Byte0 = 0x76342501,
+ .EmcSwizzleRank0Byte1 = 0x56243701,
+ .EmcSwizzleRank0Byte2 = 0x34267510,
+ .EmcSwizzleRank0Byte3 = 0x45763210,
+ .EmcSwizzleRank1Byte0 = 0x72345601,
+ .EmcSwizzleRank1Byte1 = 0x23456701,
+ .EmcSwizzleRank1Byte2 = 0x65427310,
+ .EmcSwizzleRank1Byte3 = 0x75432610,
+ .EmcTxdsrvttgen = 0x00000000,
+ .EmcDataBrlshft0 = 0x00249249,
+ .EmcDataBrlshft1 = 0x00249249,
+ .EmcDqsBrlshft0 = 0x00000000,
+ .EmcDqsBrlshft1 = 0x00000000,
+ .EmcCmdBrlshft0 = 0x00000000,
+ .EmcCmdBrlshft1 = 0x00000000,
+ .EmcCmdBrlshft2 = 0x00000012,
+ .EmcCmdBrlshft3 = 0x00000012,
+ .EmcQuseBrlshft0 = 0x00000000,
+ .EmcQuseBrlshft1 = 0x00000000,
+ .EmcQuseBrlshft2 = 0x00000000,
+ .EmcQuseBrlshft3 = 0x00000000,
+ .EmcDllCfg0 = 0x1f13412f,
+ .EmcDllCfg1 = 0x00010014,
+ .EmcPmcScratch1 = 0x4bafffff,
+ .EmcPmcScratch2 = 0x7fffffff,
+ .EmcPmcScratch3 = 0x4005d70b,
+ .EmcPmacroPadCfgCtrl = 0x00020000,
+ .EmcPmacroVttgenCtrl0 = 0x00030808,
+ .EmcPmacroVttgenCtrl1 = 0x00015000,
+ .EmcPmacroVttgenCtrl2 = 0x00101010,
+ .EmcPmacroBrickCtrlRfu1 = 0x00001600,
+ .EmcPmacroCmdBrickCtrlFdpd = 0x00000000,
+ .EmcPmacroBrickCtrlRfu2 = 0x00000000,
+ .EmcPmacroDataBrickCtrlFdpd = 0x00000000,
+ .EmcPmacroBgBiasCtrl0 = 0x00000030,
+ .EmcPmacroDataPadRxCtrl = 0x10050037,
+ .EmcPmacroCmdPadRxCtrl = 0x00000000,
+ .EmcPmacroDataRxTermMode = 0x00000010,
+ .EmcPmacroCmdRxTermMode = 0x00003000,
+ .EmcPmacroDataPadTxCtrl = 0x02000111,
+ .EmcPmacroCommonPadTxCtrl = 0x00000008,
+ .EmcPmacroCmdPadTxCtrl = 0x0a000000,
+ .EmcCfg3 = 0x00000040,
+ .EmcPmacroTxPwrd0 = 0x10000000,
+ .EmcPmacroTxPwrd1 = 0x08000000,
+ .EmcPmacroTxPwrd2 = 0x08000000,
+ .EmcPmacroTxPwrd3 = 0x08000000,
+ .EmcPmacroTxPwrd4 = 0x00000000,
+ .EmcPmacroTxPwrd5 = 0x00000000,
+ .EmcConfigSampleDelay = 0x00000020,
+ .EmcPmacroBrickMapping0 = 0x28190081,
+ .EmcPmacroBrickMapping1 = 0x44a53293,
+ .EmcPmacroBrickMapping2 = 0x76b76a5b,
+ .EmcPmacroTxSelClkSrc0 = 0x00000000,
+ .EmcPmacroTxSelClkSrc1 = 0x00000000,
+ .EmcPmacroTxSelClkSrc2 = 0x00000000,
+ .EmcPmacroTxSelClkSrc3 = 0x00000000,
+ .EmcPmacroTxSelClkSrc4 = 0x00000000,
+ .EmcPmacroTxSelClkSrc5 = 0x00000000,
+ .EmcPmacroDdllBypass = 0xefffefff,
+ .EmcPmacroDdllPwrd0 = 0xc0c0c0c0,
+ .EmcPmacroDdllPwrd1 = 0xc0c0c0c0,
+ .EmcPmacroDdllPwrd2 = 0xdcdcdcdc,
+ .EmcPmacroCmdCtrl0 = 0x0a0a0a0a,
+ .EmcPmacroCmdCtrl1 = 0x0a0a0a0a,
+ .EmcPmacroCmdCtrl2 = 0x0a0a0a0a,
+ .McEmemAdrCfg = 0x00000001,
+ .McEmemAdrCfgDev0 = 0x00070302,
+ .McEmemAdrCfgDev1 = 0x00070302,
+ .McEmemAdrCfgChannelMask = 0xffff2400,
+ .McEmemAdrCfgBankMask0 = 0x6e574400,
+ .McEmemAdrCfgBankMask1 = 0x39722800,
+ .McEmemAdrCfgBankMask2 = 0x4b9c1000,
+ .McEmemCfg = 0x00001000,
+ .McEmemArbCfg = 0x08000001,
+ .McEmemArbOutstandingReq = 0x8000004c,
+ .McEmemArbRefpbHpCtrl = 0x000a1020,
+ .McEmemArbRefpbBankCtrl = 0x80001028,
+ .McEmemArbTimingRcd = 0x00000001,
+ .McEmemArbTimingRp = 0x00000000,
+ .McEmemArbTimingRc = 0x00000003,
+ .McEmemArbTimingRas = 0x00000001,
+ .McEmemArbTimingFaw = 0x00000002,
+ .McEmemArbTimingRrd = 0x00000001,
+ .McEmemArbTimingRap2Pre = 0x00000002,
+ .McEmemArbTimingWap2Pre = 0x00000005,
+ .McEmemArbTimingR2R = 0x00000001,
+ .McEmemArbTimingW2W = 0x00000001,
+ .McEmemArbTimingR2W = 0x00000004,
+ .McEmemArbTimingW2R = 0x00000005,
+ .McEmemArbTimingRFCPB = 0x00000004,
+ .McEmemArbDaTurns = 0x02020000,
+ .McEmemArbDaCovers = 0x00030201,
+ .McEmemArbMisc0 = 0x71c30504,
+ .McEmemArbMisc1 = 0x70000f0f,
+ .McEmemArbMisc2 = 0x00000000,
+ .McEmemArbRing1Throttle = 0x001f0000,
+ .McEmemArbOverride = 0x10000000,
+ .McEmemArbOverride1 = 0x00000000,
+ .McEmemArbRsv = 0xff00ff00,
+ .McDaCfg0 = 0x00000001,
+ .McEmemArbTimingCcdmw = 0x00000008,
+ .McClkenOverride = 0x00008000,
+ .McStatControl = 0x00000000,
+ .McVideoProtectBom = 0xfff00000,
+ .McVideoProtectBomAdrHi = 0x00000000,
+ .McVideoProtectSizeMb = 0x00000000,
+ .McVideoProtectVprOverride = 0xe4bac343,
+ .McVideoProtectVprOverride1 = 0x00001ed3,
+ .McVideoProtectGpuOverride0 = 0x00000000,
+ .McVideoProtectGpuOverride1 = 0x00000000,
+ .McSecCarveoutBom = 0xfff00000,
+ .McSecCarveoutAdrHi = 0x00000000,
+ .McSecCarveoutSizeMb = 0x00000000,
+ .McVideoProtectWriteAccess = 0x00000000,
+ .McSecCarveoutProtectWriteAccess = 0x00000000,
+ .McGeneralizedCarveout1Bom = 0x00000000,
+ .McGeneralizedCarveout1BomHi = 0x00000000,
+ .McGeneralizedCarveout1Size128kb = 0x00000008,
+ .McGeneralizedCarveout1Access0 = 0x00000000,
+ .McGeneralizedCarveout1Access1 = 0x00000000,
+ .McGeneralizedCarveout1Access2 = 0x00300000,
+ .McGeneralizedCarveout1Access3 = 0x03000000,
+ .McGeneralizedCarveout1Access4 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout1ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout1Cfg0 = 0x04000c75,
+ .McGeneralizedCarveout2Bom = 0x00000000,
+ .McGeneralizedCarveout2BomHi = 0x00000000,
+ .McGeneralizedCarveout2Size128kb = 0x00000002,
+ .McGeneralizedCarveout2Access0 = 0x00000000,
+ .McGeneralizedCarveout2Access1 = 0x00000000,
+ .McGeneralizedCarveout2Access2 = 0x03000000,
+ .McGeneralizedCarveout2Access3 = 0x00000000,
+ .McGeneralizedCarveout2Access4 = 0x00000300,
+ .McGeneralizedCarveout2ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout2ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout2Cfg0 = 0x0440167c,
+ .McGeneralizedCarveout3Bom = 0x00000000,
+ .McGeneralizedCarveout3BomHi = 0x00000000,
+ .McGeneralizedCarveout3Size128kb = 0x00000000,
+ .McGeneralizedCarveout3Access0 = 0x00000000,
+ .McGeneralizedCarveout3Access1 = 0x00000000,
+ .McGeneralizedCarveout3Access2 = 0x03000000,
+ .McGeneralizedCarveout3Access3 = 0x00000000,
+ .McGeneralizedCarveout3Access4 = 0x00000300,
+ .McGeneralizedCarveout3ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout3ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout3Cfg0 = 0x04401e7c,
+ .McGeneralizedCarveout4Bom = 0x00000000,
+ .McGeneralizedCarveout4BomHi = 0x00000000,
+ .McGeneralizedCarveout4Size128kb = 0x00000008,
+ .McGeneralizedCarveout4Access0 = 0x00000000,
+ .McGeneralizedCarveout4Access1 = 0x00000000,
+ .McGeneralizedCarveout4Access2 = 0x00300000,
+ .McGeneralizedCarveout4Access3 = 0x00000000,
+ .McGeneralizedCarveout4Access4 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout4ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout4Cfg0 = 0x04002442,
+ .McGeneralizedCarveout5Bom = 0x00000000,
+ .McGeneralizedCarveout5BomHi = 0x00000000,
+ .McGeneralizedCarveout5Size128kb = 0x00000008,
+ .McGeneralizedCarveout5Access0 = 0x00000000,
+ .McGeneralizedCarveout5Access1 = 0x00000000,
+ .McGeneralizedCarveout5Access2 = 0x00300000,
+ .McGeneralizedCarveout5Access3 = 0x00000000,
+ .McGeneralizedCarveout5Access4 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess0 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess1 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess2 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess3 = 0x00000000,
+ .McGeneralizedCarveout5ForceInternalAccess4 = 0x00000000,
+ .McGeneralizedCarveout5Cfg0 = 0x04002c42,
+ .EmcCaTrainingEnable = 0x00000000,
+ .SwizzleRankByteEncode = 0x0000002e,
+ .BootRomPatchControl = 0x00000000,
+ .BootRomPatchData = 0x00000000,
+ .McMtsCarveoutBom = 0xfff00000,
+ .McMtsCarveoutAdrHi = 0x00000000,
+ .McMtsCarveoutSizeMb = 0x00000000,
+ .McMtsCarveoutRegCtrl = 0x00000000,
+},
diff --git a/src/mainboard/google/smaug/bct/sdram-unused.inc b/src/mainboard/google/smaug/bct/sdram-unused.inc
new file mode 100644
index 0000000000..bef63dcecc
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/sdram-unused.inc
@@ -0,0 +1,4 @@
+{ /* dummy. */
+ .MemoryType = NvBootMemoryType_Unused,
+ 0,
+},
diff --git a/src/mainboard/google/smaug/bct/spi.cfg b/src/mainboard/google/smaug/bct/spi.cfg
new file mode 100644
index 0000000000..63e2750efa
--- /dev/null
+++ b/src/mainboard/google/smaug/bct/spi.cfg
@@ -0,0 +1,16 @@
+# Copyright 2015 Google Inc. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00210001;
+BlockSize = 32768;
+PageSize = 2048;
+PartitionSize = 4194304;
+
+#
+# T210 bct only supports one boot device
+#
+DevType[0] = NvBootDevType_Spi;
+DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
diff --git a/src/mainboard/google/smaug/boardid.c b/src/mainboard/google/smaug/boardid.c
new file mode 100644
index 0000000000..525d1f1cae
--- /dev/null
+++ b/src/mainboard/google/smaug/boardid.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <soc/sdram.h>
+#include <stdlib.h>
+
+#include "gpio.h"
+
+uint8_t board_id(void)
+{
+ static int id = -1;
+
+ if (id < 0) {
+ gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */
+
+ id = gpio_base3_value(gpio, ARRAY_SIZE(gpio));
+ }
+
+ return id;
+}
+
+uint32_t ram_code(void)
+{
+ return sdram_get_ram_code();
+}
diff --git a/src/mainboard/google/smaug/bootblock.c b/src/mainboard/google/smaug/bootblock.c
new file mode 100644
index 0000000000..ee535c25b8
--- /dev/null
+++ b/src/mainboard/google/smaug/bootblock.c
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <soc/addressmap.h>
+#include <soc/clk_rst.h>
+#include <soc/clock.h>
+#include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/padconfig.h>
+#include <soc/pmc.h>
+#include <soc/power.h>
+#include <soc/spi.h>
+
+#include "pmic.h"
+
+/********************** PMIC **********************************/
+static const struct pad_config pmic_pads[] = {
+ PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
+ PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
+};
+
+/********************** SPI Flash *****************************/
+static const struct pad_config spiflash_pads[] = {
+ /* QSPI fLash: mosi, miso, clk, cs0, hold, wp */
+ PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+ PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+ PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE, QSPI),
+ PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE, QSPI),
+ PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+ PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
+};
+
+/********************* TPM ************************************/
+static const struct pad_config tpm_pads[] = {
+ PAD_CFG_SFIO(GEN3_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
+ PAD_CFG_SFIO(GEN3_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
+};
+
+/********************* EC *************************************/
+static const struct pad_config ec_i2c_pads[] = {
+ PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_INPUT_ENABLE, I2C2),
+ PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_INPUT_ENABLE, I2C2),
+};
+
+/********************* Funits *********************************/
+static const struct funit_cfg funits[] = {
+ /* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
+ FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
+ /* SPI flash at 24MHz on QSPI controller. */
+ FUNIT_CFG(QSPI, PLLP, 24000, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
+ /* TPM on I2C3 @ 400kHz */
+ FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
+ /* EC on I2C2 - pulled to 3.3V @ 100kHz */
+ FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)),
+};
+
+/********************* UART ***********************************/
+static const struct pad_config uart_console_pads[] = {
+ /* UARTA: tx, rx, rts, cts */
+ PAD_CFG_SFIO(UART1_TX, PINMUX_PULL_NONE, UARTA),
+ PAD_CFG_SFIO(UART1_RX, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UARTA),
+ PAD_CFG_SFIO(UART1_RTS, PINMUX_PULL_UP, UARTA),
+ PAD_CFG_SFIO(UART1_CTS, PINMUX_PULL_UP, UARTA),
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
+}
+
+static void set_clock_sources(void)
+{
+ /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
+ write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
+}
+
+/********************* PADs ***********************************/
+static const struct pad_config padcfgs[] = {
+ /* Board build id bits 1:0 */
+ PAD_CFG_GPIO_INPUT(GPIO_PK1, PINMUX_PULL_NONE),
+ PAD_CFG_GPIO_INPUT(GPIO_PK0, PINMUX_PULL_NONE),
+};
+
+void bootblock_mainboard_init(void)
+{
+ set_clock_sources();
+
+ /* Set up the pads required to load romstage. */
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+ soc_configure_funits(funits, ARRAY_SIZE(funits));
+
+ /* PMIC */
+ i2c_init(I2CPWR_BUS);
+ pmic_init(I2CPWR_BUS);
+
+ /* TPM */
+ i2c_init(I2C3_BUS);
+
+ /* EC */
+ i2c_init(I2C2_BUS);
+
+ /*
+ * Set power detect override for GPIO, audio & sdmmc3 rails.
+ * GPIO rail override is required to put it into 1.8V mode.
+ */
+ pmc_override_pwr_det(PMC_GPIO_RAIL_AO_MASK | PMC_AUDIO_RAIL_AO_MASK |
+ PMC_SDMMC3_RAIL_AO_MASK, PMC_GPIO_RAIL_AO_DISABLE |
+ PMC_AUDIO_RAIL_AO_DISABLE |
+ PMC_SDMMC3_RAIL_AO_DISABLE);
+}
diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c
new file mode 100644
index 0000000000..8ae5ac09ae
--- /dev/null
+++ b/src/mainboard/google/smaug/chromeos.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "gpio.h"
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ int count = 0;
+
+ /* Write Protect: active low */
+ gpios->gpios[count].port = WRITE_PROTECT_L;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = gpio_get(WRITE_PROTECT_L);
+ strncpy((char *)gpios->gpios[count].name, "write protect",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Recovery: active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "recovery",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* TODO(furquan): add lid switch */
+
+ /* Power: active low / high depending on board id */
+ gpios->gpios[count].port = POWER_BUTTON;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "power",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Developer: virtual GPIO active high */
+ gpios->gpios[count].port = -1;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[count].name, "developer",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* EC in RW: active high */
+ gpios->gpios[count].port = EC_IN_RW;
+ gpios->gpios[count].polarity = ACTIVE_HIGH;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "EC in RW",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ /* Reset: active low (output) */
+ gpios->gpios[count].port = AP_SYS_RESET_L;
+ gpios->gpios[count].polarity = ACTIVE_LOW;
+ gpios->gpios[count].value = -1;
+ strncpy((char *)gpios->gpios[count].name, "reset",
+ GPIO_MAX_NAME_LENGTH);
+ count++;
+
+ gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
+ gpios->count = count;
+
+ printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ uint32_t ec_events;
+
+ ec_events = google_chromeec_get_events_b();
+
+ /* Enter recovery mode either on keyboard recovery / fastboot event. */
+ return !!((ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)) ||
+ (ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)));
+}
+
+int get_write_protect_state(void)
+{
+ return !gpio_get(WRITE_PROTECT_L);
+}
diff --git a/src/mainboard/google/smaug/devicetree.cb b/src/mainboard/google/smaug/devicetree.cb
new file mode 100644
index 0000000000..65f02b2a70
--- /dev/null
+++ b/src/mainboard/google/smaug/devicetree.cb
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2015 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+chip soc/nvidia/tegra210
+ register "spintable_addr" = "0x80000008"
+
+ device cpu_cluster 0 on
+ device cpu 0 on end
+ end
+
+ register "display_controller" = "TEGRA_ARM_DISPLAYA"
+ register "xres" = "2560"
+ register "yres" = "1800"
+
+ # bits per pixel and color depth
+ register "framebuffer_bits_per_pixel" = "32"
+ register "color_depth" = "12"
+
+ # framebuffer resolution
+ register "display_xres" = "1280"
+ register "display_yres" = "800"
+
+ register "href_to_sync" = "1"
+ register "hfront_porch" = "80"
+ register "hsync_width" = "80"
+ register "hback_porch" = "80"
+
+ register "vref_to_sync" = "1"
+ register "vfront_porch" = "4"
+ register "vsync_width" = "4"
+ register "vback_porch" = "4"
+ register "refresh" = "60"
+
+ # use value from kernel driver
+ register "pixel_clock" = "304416000"
+ register "win_opt" = "DSI_ENABLE"
+end
diff --git a/src/mainboard/google/smaug/gpio.h b/src/mainboard/google/smaug/gpio.h
new file mode 100644
index 0000000000..2574c4facc
--- /dev/null
+++ b/src/mainboard/google/smaug/gpio.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_SMAUG_GPIO_H__
+#define __MAINBOARD_GOOGLE_SMAUG_GPIO_H__
+
+#include <gpio.h>
+#include <base3.h>
+
+/* Board ID definitions. */
+enum {
+ BOARD_REV0 = BASE3(0, 0),
+ BOARD_REV1 = BASE3(0, 1),
+ BOARD_REV2 = BASE3(0, Z),
+ BOARD_REV3 = BASE3(1, 0),
+ BOARD_REV4 = BASE3(1, 1),
+ BOARD_REV5 = BASE3(1, Z),
+ BOARD_REV6 = BASE3(Z, 0),
+ BOARD_REV7 = BASE3(Z, 1),
+ BOARD_REV8 = BASE3(Z, Z),
+
+ BOARD_ID_PROTO_0 = BOARD_REV0,
+ BOARD_ID_PROTO_1 = BOARD_REV1,
+ BOARD_ID_EVT = BOARD_REV2,
+ BOARD_ID_DVT = BOARD_REV3,
+ BOARD_ID_PVT = BOARD_REV4,
+ BOARD_ID_MP = BOARD_REV5,
+};
+
+enum {
+ /* Board ID related GPIOS. */
+ BD_ID0 = GPIO(K0),
+ BD_ID1 = GPIO(K1),
+
+ /* Warm reset */
+ AP_SYS_RESET_L = GPIO(M5),
+
+ /* Write Protect */
+ SPI_1V8_WP_L = GPIO(K2),
+ WRITE_PROTECT_L = SPI_1V8_WP_L,
+
+ /* Power button */
+ BTN_AP_PWR_L = GPIO(X5),
+ POWER_BUTTON = BTN_AP_PWR_L,
+
+ /* EC in RW signal */
+ EC_IN_RW = GPIO(E3),
+
+ /* Panel related GPIOs */
+ LCD_EN = GPIO(V1),
+ LCD_RST_L = GPIO(V2),
+ EN_VDD18_LCD = GPIO(V3),
+ EN_VDD_LCD = GPIO(V4),
+};
+
+#endif /* __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ */
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
new file mode 100644
index 0000000000..1a197b47f0
--- /dev/null
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <arch/mmu.h>
+#include <boot/coreboot_tables.h>
+#include <device/device.h>
+#include <device/i2c.h>
+#include <soc/addressmap.h>
+#include <soc/clk_rst.h>
+#include <soc/clock.h>
+#include <soc/funitcfg.h>
+#include <soc/padconfig.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/nvidia/tegra/pingroup.h>
+#include <soc/nvidia/tegra/dc.h>
+#include <soc/display.h>
+#include <soc/mtc.h>
+#include <soc/pmc.h>
+#include <soc/power.h>
+
+#if IS_ENABLED(CONFIG_CHROMEOS)
+#include <vendorcode/google/chromeos/vboot_handoff.h>
+#include <vendorcode/google/chromeos/vboot2/misc.h>
+#endif
+#include <delay.h>
+
+#include "gpio.h"
+#include "pmic.h"
+
+static const struct pad_config padcfgs[] = {
+ PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_NONE | PINMUX_PARKED |
+ PINMUX_INPUT_ENABLE | PINMUX_LPDR | PINMUX_IO_HV),
+};
+
+static const struct pad_config audio_codec_pads[] = {
+ /* GPIO_X1_AUD(BB3) is CODEC_RST_L and DMIC1_DAT(E1) is AUDIO_ENABLE */
+ PAD_CFG_GPIO_OUT1(GPIO_X1_AUD, PINMUX_PULL_DOWN),
+ PAD_CFG_GPIO_OUT1(DMIC1_DAT, PINMUX_PULL_DOWN),
+};
+
+static const struct pad_config i2s1_pad[] = {
+ /* I2S1 */
+ PAD_CFG_SFIO(DAP1_SCLK, PINMUX_INPUT_ENABLE, I2S1),
+ PAD_CFG_SFIO(DAP1_FS, PINMUX_INPUT_ENABLE, I2S1),
+ PAD_CFG_SFIO(DAP1_DOUT, PINMUX_INPUT_ENABLE, I2S1),
+ PAD_CFG_SFIO(DAP1_DIN, PINMUX_INPUT_ENABLE | PINMUX_TRISTATE, I2S1),
+ /* codec MCLK via AUD SFIO */
+ PAD_CFG_SFIO(AUD_MCLK, PINMUX_PULL_NONE, AUD),
+};
+
+static const struct funit_cfg audio_funit[] = {
+ /* We need 1.5MHz for I2S1. So we use CLK_M */
+ FUNIT_CFG(I2S1, CLK_M, 1500, i2s1_pad, ARRAY_SIZE(i2s1_pad)),
+};
+
+static const struct funit_cfg funits[] = {
+ FUNIT_CFG_USB(USBD),
+ FUNIT_CFG(SDMMC4, PLLP, 48000, NULL, 0),
+ /* I2C6 for audio, temp sensor, etc. Enable codec via GPIOs/muxes */
+ FUNIT_CFG(I2C6, PLLP, 400, audio_codec_pads, ARRAY_SIZE(audio_codec_pads)),
+};
+
+/* Audio init: clocks and enables/resets */
+static void setup_audio(void)
+{
+ /* Audio codec (RT5677) uses 12MHz CLK1/EXTPERIPH1 */
+ clock_configure_source(extperiph1, PLLP, 12000);
+
+ /* Configure AUD_MCLK pad drive strength */
+ write32((unsigned int *)TEGRA_APB_MISC_GP_BASE + 0xF4,
+ (0x10 << PINGROUP_DRVUP_SHIFT | 0x10 << PINGROUP_DRVDN_SHIFT));
+
+ /* Set up audio peripheral clocks/muxes */
+ soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
+
+ /* Enable CLK1_OUT */
+ clock_external_output(1);
+
+ /*
+ * As per NVIDIA hardware team, we need to take ALL audio devices
+ * connected to AHUB (AUDIO, APB2APE, I2S, SPDIF, etc.) out of reset
+ * and clock-enabled, otherwise reading AHUB devices (in our case,
+ * I2S/APBIF/AUDIO<XBAR>) will hang.
+ */
+ soc_configure_ape();
+ clock_enable_audio();
+}
+
+static const struct pad_config lcd_gpio_padcfgs[] = {
+ /* LCD_EN */
+ PAD_CFG_GPIO_OUT0(LCD_BL_EN, PINMUX_PULL_UP),
+ /* LCD_RST_L */
+ PAD_CFG_GPIO_OUT0(LCD_RST, PINMUX_PULL_UP),
+ /* EN_VDD_LCD */
+ PAD_CFG_GPIO_OUT0(LCD_GPIO2, PINMUX_PULL_NONE),
+ /* EN_VDD18_LCD */
+ PAD_CFG_GPIO_OUT0(LCD_GPIO1, PINMUX_PULL_NONE),
+};
+
+static void configure_display_clocks(void)
+{
+ u32 lclks = CLK_L_HOST1X | CLK_L_DISP1; /* dc */
+ u32 hclks = CLK_H_MIPI_CAL | CLK_H_DSI; /* mipi phy, mipi-dsi a */
+ u32 uclks = CLK_U_DSIB; /* mipi-dsi b */
+ u32 xclks = CLK_X_UART_FST_MIPI_CAL; /* uart_fst_mipi_cal */
+
+ clock_enable_clear_reset(lclks, hclks, uclks, 0, 0, xclks, 0);
+
+ /* Give clocks time to stabilize. */
+ udelay(IO_STABILIZATION_DELAY);
+
+ /* CLK72MHZ_CLK_SRC */
+ clock_configure_source(uart_fst_mipi_cal, PLLP_OUT3, 68000);
+}
+
+static int enable_lcd_vdd(void)
+{
+ /* Set 1.20V to power AVDD_DSI_CSI */
+ /* LD0: 1.20v CNF1: 0x0d */
+ pmic_write_reg_77620(I2CPWR_BUS, MAX77620_CNFG1_L0_REG, 0xd0, 1);
+
+ /* Enable VDD_LCD */
+ gpio_set(EN_VDD_LCD, 1);
+ /* wait for 2ms */
+ mdelay(2);
+
+ /* Enable PP1800_LCDIO to panel */
+ gpio_set(EN_VDD18_LCD, 1);
+ /* wait for 1ms */
+ mdelay(1);
+
+ /* Set panel EN and RST signals */
+ gpio_set(LCD_EN, 1); /* enable */
+ /* wait for min 10ms */
+ mdelay(10);
+ gpio_set(LCD_RST_L, 1); /* clear reset */
+ /* wait for min 3ms */
+ mdelay(3);
+
+ return 0;
+}
+
+static int configure_display_blocks(void)
+{
+ /* enable display related clocks */
+ configure_display_clocks();
+
+ /* configure panel gpio pads */
+ soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
+
+ /* set and enable panel related vdd */
+ if (enable_lcd_vdd())
+ return -1;
+
+ return 0;
+}
+
+static void powergate_unused_partitions(void)
+{
+ static const uint32_t partitions[] = {
+ POWER_PARTID_PCX,
+ POWER_PARTID_SAX,
+ POWER_PARTID_NVDEC,
+ POWER_PARTID_NVJPG,
+ POWER_PARTID_DFD,
+ };
+
+ int i;
+ for (i = 0; i < ARRAY_SIZE(partitions); i++)
+ power_gate_partition(partitions[i]);
+}
+
+static void mainboard_init(device_t dev)
+{
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+ soc_configure_funits(funits, ARRAY_SIZE(funits));
+
+ /* I2C6 bus (audio, etc.) */
+ soc_configure_i2c6pad();
+ i2c_init(I2C6_BUS);
+ setup_audio();
+
+ /* if panel needs to bringup */
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ if (!vboot_skip_display_init())
+#endif
+ configure_display_blocks();
+
+ powergate_unused_partitions();
+}
+
+void display_startup(device_t dev)
+{
+ dsi_display_startup(dev);
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "smaug",
+ .enable_dev = mainboard_enable,
+};
+
+void lb_board(struct lb_header *header)
+{
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ lb_table_add_serialno_from_vpd(header);
+#endif
+ soc_add_mtc(header);
+}
diff --git a/src/mainboard/google/smaug/memlayout.ld b/src/mainboard/google/smaug/memlayout.ld
new file mode 100644
index 0000000000..a71dcb8508
--- /dev/null
+++ b/src/mainboard/google/smaug/memlayout.ld
@@ -0,0 +1,6 @@
+#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
+#include <soc/memlayout_vboot2.ld>
+#else
+#include <soc/memlayout.ld>
+#endif
+
diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c
new file mode 100644
index 0000000000..17d65e5ec3
--- /dev/null
+++ b/src/mainboard/google/smaug/pmic.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/i2c.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "pmic.h"
+#include "reset.h"
+
+enum {
+ MAX77620_I2C_ADDR = 0x3c,
+ MAX77621_CPU_I2C_ADDR = 0x1B,
+ MAX77621_GPU_I2C_ADDR = 0x1C,
+};
+
+struct max77620_init_reg {
+ u8 reg;
+ u8 val;
+ u8 delay;
+};
+
+static struct max77620_init_reg init_list[] = {
+ /* TODO */
+};
+
+static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val,
+ int delay)
+{
+ if (i2c_writeb(bus, chip, reg, val)) {
+ printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
+ __func__, reg, val);
+ /* Reset the SoC on any PMIC write error */
+ cpu_reset();
+ } else {
+ if (delay)
+ udelay(500);
+ }
+}
+
+void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val,
+ int delay)
+{
+ pmic_write_reg(bus, MAX77620_I2C_ADDR, reg, val, delay);
+}
+
+static inline void pmic_write_reg_77621(unsigned bus, uint8_t reg, uint8_t val,
+ int delay)
+{
+ pmic_write_reg(bus, MAX77621_CPU_I2C_ADDR, reg, val, delay);
+}
+
+static void pmic_slam_defaults(unsigned bus)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(init_list); i++) {
+ struct max77620_init_reg *reg = &init_list[i];
+ pmic_write_reg_77620(bus, reg->reg, reg->val, reg->delay);
+ }
+}
+
+void pmic_init(unsigned bus)
+{
+ /* Restore PMIC POR defaults, in case kernel changed 'em */
+ pmic_slam_defaults(bus);
+
+ /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
+ pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1);
+
+ /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN -- ??? */
+ pmic_write_reg_77620(bus, MAX77620_GPIO1_REG, 0x09, 1);
+
+ /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
+ pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x1c, 1);
+
+ /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v? */
+ pmic_write_reg_77620(bus, MAX77620_CNFG2SD_REG, 0x04, 1);
+
+ pmic_write_reg_77620(bus, MAX77620_SD1_REG, 0x2a, 1);
+
+ /* Max77621 VREG for CPU needs to be set to 0.85V as per SysEng */
+
+ /* Max77621 CPU VREG, register 0, 0.85V = 0x27(0.60625 + (39*6.25mV)) */
+ pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0x27, 1);
+ pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xa7, 1);
+
+ /* Max77621 CPU VREG DVC, register 1, 0.85V = 0x27 */
+ pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0x27, 1);
+ pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xa7, 1);
+
+ printk(BIOS_DEBUG, "PMIC init done\n");
+}
diff --git a/src/mainboard/google/smaug/pmic.h b/src/mainboard/google/smaug/pmic.h
new file mode 100644
index 0000000000..d38b3282b7
--- /dev/null
+++ b/src/mainboard/google/smaug/pmic.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
+#define __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
+
+#define MAX77620_SD0_REG 0x16
+#define MAX77620_SD1_REG 0x17
+#define MAX77620_SD2_REG 0x18
+#define MAX77620_SD3_REG 0x19
+#define MAX77620_CNFG2SD_REG 0x22
+
+#define MAX77620_CNFG1_L0_REG 0x23
+#define MAX77620_CNFG2_L0_REG 0x24
+#define MAX77620_CNFG1_L1_REG 0x25
+#define MAX77620_CNFG2_L1_REG 0x26
+#define MAX77620_CNFG1_L2_REG 0x27
+#define MAX77620_CNFG2_L2_REG 0x28
+#define MAX77620_CNFG1_L3_REG 0x29
+#define MAX77620_CNFG2_L3_REG 0x2A
+#define MAX77620_CNFG1_L4_REG 0x2B
+#define MAX77620_CNFG2_L4_REG 0x2C
+#define MAX77620_CNFG1_L5_REG 0x2D
+#define MAX77620_CNFG2_L5_REG 0x2E
+#define MAX77620_CNFG1_L6_REG 0x2F
+#define MAX77620_CNFG2_L6_REG 0x30
+#define MAX77620_CNFG1_L7_REG 0x31
+#define MAX77620_CNFG2_L7_REG 0x32
+#define MAX77620_CNFG1_L8_REG 0x33
+#define MAX77620_CNFG2_L8_REG 0x34
+#define MAX77620_CNFG3_LDO_REG 0x35
+
+#define MAX77620_GPIO0_REG 0x36
+#define MAX77620_GPIO1_REG 0x37
+#define MAX77620_GPIO2_REG 0x38
+#define MAX77620_GPIO3_REG 0x39
+#define MAX77620_GPIO4_REG 0x3A
+#define MAX77620_GPIO5_REG 0x3B
+#define MAX77620_GPIO6_REG 0x3C
+#define MAX77620_GPIO7_REG 0x3D
+#define MAX77620_GPIO_PUE_GPIO 0x3E
+#define MAX77620_GPIO_PDE_GPIO 0x3F
+
+#define MAX77620_AME_GPIO 0x40
+#define MAX77620_REG_ONOFF_CFG1 0x41
+#define MAX77620_REG_ONOFF_CFG2 0x42
+
+#define MAX77620_CID0_REG 0x58
+#define MAX77620_CID1_REG 0x59
+#define MAX77620_CID2_REG 0x5A
+#define MAX77620_CID3_REG 0x5B
+#define MAX77620_CID4_REG 0x5C
+#define MAX77620_CID5_REG 0x5D
+
+#define MAX77621_VOUT_REG 0x00
+#define MAX77621_VOUT_DVC_REG 0x01
+
+void pmic_init(unsigned bus);
+void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val,
+ int delay);
+
+#endif /* __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ */
diff --git a/src/mainboard/google/smaug/reset.c b/src/mainboard/google/smaug/reset.c
new file mode 100644
index 0000000000..9c72a77300
--- /dev/null
+++ b/src/mainboard/google/smaug/reset.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+#include "gpio.h"
+
+void hard_reset(void)
+{
+ gpio_output(AP_SYS_RESET_L, 0);
+ while (1)
+ ;
+}
diff --git a/src/mainboard/google/smaug/romstage.c b/src/mainboard/google/smaug/romstage.c
new file mode 100644
index 0000000000..5229a9ffc2
--- /dev/null
+++ b/src/mainboard/google/smaug/romstage.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <device/i2c.h>
+#include <soc/clock.h>
+#include <soc/funitcfg.h>
+#include <soc/nvidia/tegra/i2c.h>
+#include <soc/padconfig.h>
+#include <soc/romstage.h>
+
+#include "gpio.h"
+#include "pmic.h"
+
+static const struct pad_config padcfgs[] = {
+ /* AP_SYS_RESET_L - active low*/
+ PAD_CFG_GPIO_OUT1(SDMMC1_DAT0, PINMUX_PULL_UP),
+ /* WP_L - active low */
+ PAD_CFG_GPIO_INPUT(GPIO_PK2, PINMUX_PULL_NONE),
+ /* BTN_AP_PWR_L - active low */
+ PAD_CFG_GPIO_INPUT(BUTTON_POWER_ON, PINMUX_PULL_UP),
+ /* BTN_AP_VOLD_L - active low */
+ PAD_CFG_GPIO_INPUT(BUTTON_VOL_DOWN, PINMUX_PULL_UP),
+ /* BTN_AP_VOLU_L - active low */
+ PAD_CFG_GPIO_INPUT(SDMMC1_DAT1, PINMUX_PULL_UP),
+};
+
+void romstage_mainboard_init(void)
+{
+ soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
+}
+
+void mainboard_configure_pmc(void)
+{
+}
+
+void mainboard_enable_vdd_cpu(void)
+{
+ /* VDD_CPU is already enabled in bootblock. */
+}
diff --git a/src/mainboard/google/smaug/sdram_configs.c b/src/mainboard/google/smaug/sdram_configs.c
new file mode 100644
index 0000000000..91e5aefdeb
--- /dev/null
+++ b/src/mainboard/google/smaug/sdram_configs.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <soc/sdram_configs.h>
+
+static struct sdram_params sdram_configs[] = {
+#include "bct/sdram-unused.inc" /* ram_code = 0000 */
+#include "bct/sdram-unused.inc" /* ram_code = 0001 */
+#include "bct/sdram-samsung-3GB-204.inc" /* ram_code = 0010 */
+#include "bct/sdram-samsung-4GB-204.inc" /* ram_code = 0011 */
+#include "bct/sdram-unused.inc" /* ram_code = 0100 */
+#include "bct/sdram-unused.inc" /* ram_code = 0101 */
+#include "bct/sdram-unused.inc" /* ram_code = 0110 */
+#include "bct/sdram-unused.inc" /* ram_code = 0111 */
+#include "bct/sdram-unused.inc" /* ram_code = 1000 */
+#include "bct/sdram-unused.inc" /* ram_code = 1001 */
+#include "bct/sdram-unused.inc" /* ram_code = 1010 */
+#include "bct/sdram-unused.inc" /* ram_code = 1011 */
+#include "bct/sdram-unused.inc" /* ram_code = 1100 */
+#include "bct/sdram-unused.inc" /* ram_code = 1101 */
+#include "bct/sdram-unused.inc" /* ram_code = 1110 */
+#include "bct/sdram-unused.inc" /* ram_code = 1111 */
+};
+
+const struct sdram_params *get_sdram_config()
+{
+ uint32_t ramcode = sdram_get_ram_code();
+ /*
+ * If we need to apply some special hacks to RAMCODE mapping (ex, by
+ * board_id), do that now.
+ */
+
+ printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
+ if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
+ sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) {
+ die("Invalid RAMCODE.");
+ }
+
+ return &sdram_configs[ramcode];
+}