diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-02-14 11:51:14 +0100 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-16 05:30:27 +0000 |
| commit | a25283d8ae905bce31d16202c4e4d4b54051ea86 (patch) | |
| tree | 5693b58b4d801c7e3f737cd6c8563acd51aac3bb /src/mainboard/google | |
| parent | e1b8221498b6742cd87271d736ffc6f8f0f82633 (diff) | |
| download | coreboot-a25283d8ae905bce31d16202c4e4d4b54051ea86.tar.xz | |
mb/google/zoombini/variants/meowth: enable FPMCU interrupt
Enable the micro-controller interrupt line as a real IRQ.
BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.
Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/gpio.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/gpio.c b/src/mainboard/google/zoombini/variants/meowth/gpio.c index 21c4bbce50..7869deafd8 100644 --- a/src/mainboard/google/zoombini/variants/meowth/gpio.c +++ b/src/mainboard/google/zoombini/variants/meowth/gpio.c @@ -40,7 +40,8 @@ static const struct pad_config gpio_table[] = { /* ISH_GP1 */ PAD_NC(GPP_A19, NONE), /* ISH_GP2 */ PAD_NC(GPP_A20, NONE), /* ISH_GP3 */ PAD_CFG_GPO(GPP_A21, 0, DEEP), /* PCH_FPMCU_BOOT0 */ -/* ISH_GP4 */ PAD_CFG_GPI(GPP_A22, NONE, DEEP), /* FPMCU_INT */ +/* ISH_GP4 */ PAD_CFG_GPI_APIC(GPP_A22, NONE, DEEP, LEVEL, + NONE), /* FPMCU_INT */ /* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_FPMCU_RST_ODL */ /* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ /* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ |