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authorYidi Lin <yidi.lin@mediatek.com>2016-01-29 17:25:03 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-03-12 09:12:13 +0100
commita622f28cb249c9d88751ce2694c83a62c25c221e (patch)
treea16fc8f7c5c83dfb118ee3c5b56bfaee034ca7ae /src/mainboard/google
parentd8bb51eb4e00882259862129325aa7bf160f79c3 (diff)
downloadcoreboot-a622f28cb249c9d88751ce2694c83a62c25c221e.tar.xz
mediatek/mt8173: pll: raising the CPU core frequency
Runs the LITTLE core at highest freqency to speed up the boot time. Set Vproc to 1.125V and set the freqency to 1.6Ghz for backward compatibility. (The highest frequency for the IC before E3 is 1.6Ghz.) BRANCH=none BUG=chrome-os-partner:47422 TEST=flash the bootloader and measure the boottime by cbmem result Change-Id: Id0b906bf34ac534667eb6e8f576e30942ceb923e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5fc38548d158158f07cded8cfc8ea5a0a7952161 Original-Change-Id: I62af26c13d98211974243100c581abcb5408fd63 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/324685 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/oak/romstage.c22
1 files changed, 21 insertions, 1 deletions
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index d72693fa4d..3d018a02b1 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -17,7 +17,7 @@
#include <arch/exception.h>
#include <arch/io.h>
#include <arch/mmu.h>
-
+#include <boardid.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
@@ -25,14 +25,20 @@
#include <program_loading.h>
#include <romstage_handoff.h>
#include <symbols.h>
+#include <timer.h>
#include <timestamp.h>
#include <soc/emi.h>
#include <soc/mmu_operations.h>
+#include <soc/mt6391.h>
+#include <soc/pll.h>
#include <soc/rtc.h>
void main(void)
{
+ int stabilize_usec;
+ struct stopwatch sw;
+
timestamp_add_now(TS_START_ROMSTAGE);
/* init uart baudrate when pll on */
@@ -41,9 +47,23 @@ void main(void)
rtc_boot();
+ /* Raise CPU voltage to allow higher frequency */
+ stabilize_usec = mt6391_configure_ca53_voltage(1125000);
+
+ stopwatch_init_usecs_expire(&sw, stabilize_usec);
+
/* init memory */
mt_mem_init(get_sdram_config());
+ while (!stopwatch_expired(&sw))
+ ;
+
+ /* Set to maximum frequency */
+ if (board_id() < 5)
+ mt_pll_raise_ca53_freq(1600 * MHz);
+ else
+ mt_pll_raise_ca53_freq(1700 * MHz);
+
mt8173_mmu_after_dram();
/* should be called after memory init */