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authorGaggery Tsai <gaggery.tsai@intel.com>2019-05-08 12:11:21 -0700
committerFurquan Shaikh <furquan@google.com>2019-05-14 23:33:45 +0000
commitd1ad37847da61d243f691590005865df505dc31f (patch)
tree860991ad8b8d1cd39a928820855819c17dc185ec /src/mainboard/google
parent97e9e5622df8b2386b2828da2671018232056035 (diff)
downloadcoreboot-d1ad37847da61d243f691590005865df505dc31f.tar.xz
mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error
This patch adds a workaround for Samsung C-die 2G/4G memory chips. For unknown reasons, some boards with Samsung LP3 memory chips could not pass early CS/CMD training. MRC has to change the granularity from 16 ticks to 8 ticks, which implies bad margin with this memory chip. Another way is to enhance the drive strength for CS. This patch is to enhance the drive strength for CS and CMD. Enhancing the drive strength for CMD could gain margin abaout 3 more ticks. Root cause needs to be further investigated with memory vendor. BUG=b:131177542 BRANCH=None TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage & check the MRC log to ensure correct Rcomp values are passed to MRC. Tested with board ID #8 and #11. Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/memory.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c
index 0b34e72830..022b733398 100644
--- a/src/mainboard/google/poppy/variants/atlas/memory.c
+++ b/src/mainboard/google/poppy/variants/atlas/memory.c
@@ -13,8 +13,11 @@
* GNU General Public License for more details.
*/
+#include <assert.h>
#include <baseboard/variants.h>
+#define SAMSUNG_C_DIE_2G 10
+#define SAMSUNG_C_DIE_4G 11
/* DQ byte map */
static const u8 dq_map[][12] = {
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -34,9 +37,12 @@ static const u16 rcomp_resistor[] = { 200, 81, 162 };
/* Rcomp target */
static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
+static const u16 rcomp_target_samsung_c_die[] = { 100, 40, 35, 18, 40 };
void variant_memory_params(struct memory_params *p)
{
+ int spd_index;
+
p->type = MEMORY_LPDDR3;
p->dq_map = dq_map;
p->dq_map_size = sizeof(dq_map);
@@ -44,6 +50,11 @@ void variant_memory_params(struct memory_params *p)
p->dqs_map_size = sizeof(dqs_map);
p->rcomp_resistor = rcomp_resistor;
p->rcomp_resistor_size = sizeof(rcomp_resistor);
- p->rcomp_target = rcomp_target;
+ spd_index = variant_memory_sku();
+ assert(spd_index >= 0);
+ if (spd_index == SAMSUNG_C_DIE_2G || spd_index == SAMSUNG_C_DIE_4G)
+ p->rcomp_target = rcomp_target_samsung_c_die;
+ else
+ p->rcomp_target = rcomp_target;
p->rcomp_target_size = sizeof(rcomp_target);
}