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authorRavi Sarawadi <ravishankar.sarawadi@intel.com>2017-08-04 16:26:09 -0700
committerAaron Durbin <adurbin@chromium.org>2017-08-15 19:59:21 +0000
commitefa606b77b93254d0e378ceab851753886f5efec (patch)
tree517952c4eb87995678b7f3ddc057bad1790d0251 /src/mainboard/google
parenta045fb9de8602ca44d312c997ee607ab86c41ba4 (diff)
downloadcoreboot-efa606b77b93254d0e378ceab851753886f5efec.tar.xz
soc/intel/common/block: Add LPC Common code and use it for APL
Add LPC common code to be shared across Intel platforms. Also add LPC library functions to be shared across platforms. Use common LPC code for Apollo Lake soc. Update existing Apollolake mainboard variants {google,intel,siemens} to use new common LPC header file. Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/reef/bootblock.c2
-rw-r--r--src/mainboard/google/reef/ec.c13
2 files changed, 8 insertions, 7 deletions
diff --git a/src/mainboard/google/reef/bootblock.c b/src/mainboard/google/reef/bootblock.c
index 57d20d9058..dd06f649e2 100644
--- a/src/mainboard/google/reef/bootblock.c
+++ b/src/mainboard/google/reef/bootblock.c
@@ -16,7 +16,7 @@
#include <baseboard/variants.h>
#include <bootblock_common.h>
#include <ec/ec.h>
-#include <soc/lpc.h>
+#include <intelblocks/lpc_lib.h>
#include <soc/gpio.h>
#include <variant/ec.h>
diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c
index 646216b8e3..59fa442414 100644
--- a/src/mainboard/google/reef/ec.c
+++ b/src/mainboard/google/reef/ec.c
@@ -17,8 +17,8 @@
#include <console/console.h>
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
+#include <intelblocks/lpc_lib.h>
#include <rules.h>
-#include <soc/lpc.h>
#include <variant/ec.h>
static void ramstage_ec_init(void)
@@ -53,11 +53,12 @@ static void bootblock_ec_init(void)
size_t ec_ioport_size;
/*
- * Set up LPC decoding for the ChromeEC I/O port ranges:
- * - Ports 62/66, 60/64, and 200->208
- * - ChromeEC specific communication I/O ports.
- */
- lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+ * Set up LPC decoding for the ChromeEC I/O port ranges:
+ * - Ports 62/66, 60/64, and 200->208
+ * - ChromeEC specific communication I/O ports.
+ */
+ lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
+ | LPC_IOE_LGE_200);
google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
}