diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-19 12:31:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-21 07:16:01 +0000 |
| commit | f50ea988b09e7201e129848ab64e6e0e69bf56c4 (patch) | |
| tree | e7cf17631d7c3cd41fa3c68a4c578d4ee7e36b8a /src/mainboard/google | |
| parent | dadcbfbe8c682c89b277fdbdfdd26cabd15fc20a (diff) | |
| download | coreboot-f50ea988b09e7201e129848ab64e6e0e69bf56c4.tar.xz | |
soc/intel,mb/*: get rid of legacy pad macros
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
18 files changed, 1543 insertions, 1544 deletions
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 21d322275e..607486be4c 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -31,69 +31,69 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP41 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP41 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */ -/* PIRQA# */ PAD_CFG_NC(GPP_A7), -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP44 */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP45 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP67 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), - -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP42 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), /* TP43 */ -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_NC(GPP_B5), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), + +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP42 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* TP43 */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD_INT_L */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE), /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), +/* SPKR */ PAD_NC(GPP_B14, NONE), /* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* DSP */ /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* DSP */ /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* DSP */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* DSP */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), - -/* SMBCLK */ PAD_CFG_NC(GPP_C0), -/* SMBDATA */ PAD_CFG_NC(GPP_C1), -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), + +/* SMBCLK */ PAD_NC(GPP_C0, NONE), +/* SMBDATA */ PAD_NC(GPP_C1, NONE), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* SM1DATA */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, @@ -109,59 +109,59 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */ /* SPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */ -/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ -/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ +/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, UP_20K, DEEP), /* EN_PP3300_DX_CAM */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */ /* USB2_OC2# */ PAD_CFG_GPO(GPP_E11, 1, DEEP), /* TOUCHSCREEN_STOP_L */ -/* USB2_OC3# */ PAD_CFG_NC(GPP_E12), -/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* USB_C0_DP_HPD */ -/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */ +/* USB2_OC3# */ PAD_NC(GPP_E12, NONE), +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* USB_C0_DP_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* USB_C1_DP_HPD */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP48 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP244 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -176,8 +176,8 @@ static const struct pad_config gpio_table[] = { DEEP), /* DISPLAY is master */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* TP109 */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* TP109 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -189,38 +189,38 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* RSVD */ PAD_NC(GPP_F23, NONE), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* ACPRESENT */ PAD_CFG_NF(GPD1, 20K_PU, DEEP, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, UP_20K, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP26 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP26 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP25 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP15 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP25 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP15 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ /* Ensure UART pins are in native mode for H1 */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index c6b0b01970..2ebc51ad04 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -7,46 +7,46 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, - EDGE), /* SD_CDZ */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP, + EDGE_SINGLE), /* SD_CDZ */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* TP333 */ +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), /* TP139 */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ @@ -61,30 +61,30 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K, DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K, DEEP), /* HWA_TRST_N */ -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP141 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K, DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K, DEEP), /* GPIO2 */ -/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, +/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, UP_20K, DEEP), /* GPIO3 */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K, DEEP), /* GPIO4 */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ @@ -96,55 +96,55 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP309 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP259 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP260 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP261 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP262 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP153 */ +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), /* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, - PLTRST, EDGE), /* HP_IRQ_GPIO */ + PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* TP121 */ +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), /* TP122 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP257 */ +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), /* TP258 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_NC(GPP_E7, NONE), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP314 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ @@ -156,46 +156,46 @@ static const struct pad_config gpio_table[] = { NF1), /* INT_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP325 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP326 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), /* TP191 */ +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), /* TP192 */ +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), /* TP190 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP189 */ /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SDA */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -204,20 +204,20 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP292 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP148 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP147 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP146 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP143 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -230,8 +230,8 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index d4be35fed3..add697f941 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -7,36 +7,36 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, EDGE), /* SD_CDZ */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), /* SD_CDZ */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ /* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */ /* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */ -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ -/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ +/* CPU_GP2 */ PAD_NC(GPP_B3, NONE), +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLK_PCIE_LAN_REQ# */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_TPU# */ @@ -51,24 +51,24 @@ static const struct pad_config gpio_table[] = { /* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_CLK */ /* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP98 */ -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP44 */ +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP98 */ +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP44 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP99 */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP99 */ +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* SKU_ID1 */ /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* SKU_ID2 */ @@ -79,85 +79,85 @@ static const struct pad_config gpio_table[] = { /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SCL */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP93 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP93 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP106 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP102 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP104 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP105 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP91 */ -/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), -/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP106 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP102 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP104 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP105 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP91 */ +/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), +/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE_SINGLE), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), -/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP100 */ -/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP90 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP101 */ -/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP94 */ +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), +/* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* TP100 */ +/* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), /* TP90 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP101 */ +/* SPI1_IO3 */ PAD_NC(GPP_D22, NONE), /* TP94 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, NONE), /* TPU_RST_PIN40 */ -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ /* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP, NONE), /* TPU_RST_PIN42 */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP96 */ +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), /* T1037 */ +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* T1025 */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* Rear Single USB Port */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI1_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HDMI_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP1021 */ +/* DDPD_HPD2 */ PAD_CFG_GPI_APIC_HIGH(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP1021 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDI2_DDCCLK_SW */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDI2_DDCDATA_SW */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP43 */ -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP48 */ -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP42 */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP37 */ -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), /* TP43 */ +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), /* TP48 */ +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), /* TP42 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP37 */ +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), /* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* DDI1_I2C_7322_SDA */ /* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */ -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), @@ -166,20 +166,20 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP40 */ +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP40 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP23 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP23 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP22 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP22 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP83 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP84 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP83 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP84 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index 309222b4f9..2735fed671 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -7,35 +7,35 @@ /* Pad configuration in ramstage */ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { -/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* RCIN# */ PAD_NC(GPP_A0, NONE), /* TP308 */ /* ESPI_IO0 */ /* ESPI_IO1 */ /* ESPI_IO2 */ /* ESPI_IO3 */ /* ESPI_CS# */ -/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_NC(GPP_A7), /* TP104 */ -/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* SERIRQ */ PAD_NC(GPP_A6, NONE), /* TP331 */ +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* TP104 */ +/* CLKRUN# */ PAD_NC(GPP_A8, NONE), /* TP329 */ /* ESPI_CLK */ -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ -/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* TP188 */ +/* PME# */ PAD_NC(GPP_A11, NONE), /* TP149 */ +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, DEEP), /* eSPI mode */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* SUSACK# */ PAD_NC(GPP_A15, NONE), /* TP150 */ +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ /* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), /* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* PCH_SPK_EN */ -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), /* TP156 */ +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), /* TP152 */ /* CPU_GP2 */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* TOUCHSCREEN_RST# */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* PCH_TS_EN */ /* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, @@ -44,8 +44,8 @@ static const struct pad_config gpio_table[] = { NF1), /* PCIE_CLKREQ_SSD# */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* PCIE_CLKREQ_NGFF1# */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* TP333 */ +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), /* TP139 */ /* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* PCIE_CLKREQ_WLAN# */ /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ @@ -60,29 +60,29 @@ static const struct pad_config gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ -/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, UP_20K, DEEP), /* VR_DISABLE_L */ -/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, UP_20K, DEEP), /* HWA_TRST_N */ -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ -/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_NC(GPP_B23, NONE), /* TP141 */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ -/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, +/* SM1DATA */ PAD_NC(GPP_C7, NONE), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, UP_20K, DEEP), /* GPIO1 */ -/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, UP_20K, DEEP), /* GPIO2 */ /* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* V3P3_CCD_EN */ -/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, UP_20K, DEEP), /* GPIO4 */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* SKU_ID0 */ @@ -94,60 +94,59 @@ static const struct pad_config gpio_table[] = { DEEP), /* SKU_ID3 */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), -/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* I2C1_SDA */ PAD_NC(GPP_C18, NONE), +/* I2C1_SCL */ PAD_NC(GPP_C19, NONE), /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ -/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* TP309 */ /* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, DEEP), /* SCREW_SPI_WP_STATUS */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), /* TP259 */ +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), /* TP260 */ +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), /* TP261 */ +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), /* TP262 */ +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* TP153 */ /* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCH_I2C0_8625_SDA */ /* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCH_I2C0_8625_SCL */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, - PLTRST), /* HP_IRQ_GPIO */ +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */ /* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* OEM_ID1 */ /* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP), /* OEM_ID2 */ /* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP), /* OEM_ID3 */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* PCH_DMIC_CLK0 */ /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* PCH_DMIC_DATA0 */ -/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ +/* SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TP257 */ /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* BOOT_BEEP_OVERRIDE */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), /* DB_PCIE_SATA#_DET */ -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, - PLTRST), /* TOUCHSCREEN_INT# */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, + NONE), /* TOUCHSCREEN_INT# */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* TP314 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* Rear Dual-Stack USB Ports */ @@ -159,12 +158,12 @@ static const struct pad_config gpio_table[] = { NF1), /* INT_HDMI_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI2_HPD */ -/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ -/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* DDPD_HPD2 */ PAD_NC(GPP_E15, NONE), /* TP325 */ +/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* TP326 */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */ -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* HDMI_DDCCLK_DATA */ /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ @@ -177,53 +176,53 @@ static const struct pad_config gpio_table[] = { DEEP), /* I2S_2_FS_LRC */ /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S_2_TX_DAC */ -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), /* TP189 */ /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SDA */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* PCH_I2C2_H1_3V3_SCL */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), -/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), +/* I2C4_SDA */ PAD_NC(GPP_F8, NONE), +/* I2C4_SCL */ PAD_NC(GPP_F9, NONE), /* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ /* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ -/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), -/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), -/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), -/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), -/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), -/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), -/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), -/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), -/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), -/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), -/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* EMMC_CMD */ PAD_NC(GPP_F12, NONE), +/* EMMC_DATA0 */ PAD_NC(GPP_F13, NONE), +/* EMMC_DATA1 */ PAD_NC(GPP_F14, NONE), +/* EMMC_DATA2 */ PAD_NC(GPP_F15, NONE), +/* EMMC_DATA3 */ PAD_NC(GPP_F16, NONE), +/* EMMC_DATA4 */ PAD_NC(GPP_F17, NONE), +/* EMMC_DATA5 */ PAD_NC(GPP_F18, NONE), +/* EMMC_DATA6 */ PAD_NC(GPP_F19, NONE), +/* EMMC_DATA7 */ PAD_NC(GPP_F20, NONE), +/* EMMC_RCLK */ PAD_NC(GPP_F21, NONE), +/* EMMC_CLK */ PAD_NC(GPP_F22, NONE), +/* RSVD */ PAD_NC(GPP_F23, NONE), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* TP292 */ -/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* BATLOW# */ PAD_NC(GPD0, NONE), /* TP148 */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PCH_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ -/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ -/* RSVD */ PAD_CFG_NC(GPD7), +/* SLP_A# */ PAD_NC(GPD6, NONE), /* TP147 */ +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ -/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), /* TP146 */ +/* SLP_S5# */ PAD_NC(GPD10, NONE), /* TP143 */ +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -236,8 +235,8 @@ static const struct pad_config early_gpio_table[] = { NF1), /* PCH_SPI_H1_3V3_MISO */ /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* PCH_SPI_H1_3V3_MOSI */ -/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, - PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST, LEVEL, + INVERT), /* H1_PCH_INT_ODL */ /* Ensure UART pins are in native mode for H1. */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index b6743dc47b..b4c65baa90 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -48,138 +48,138 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2 */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SRCCLKREQ4 */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -192,14 +192,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -207,16 +207,16 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 1f4bd6565a..24e7b33cc2 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -57,64 +57,64 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), /* SD_CD_INT_L */ +/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* SD_CD_INT_L */ /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_GPI_ACPI_SCI(GPP_B15, NONE, DEEP, NONE), /* DIG EJECT */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_CFG_GPI_SCI(GPP_B15, NONE, DEEP, EDGE_SINGLE, NONE), /* DIG EJECT */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* non-wake DIG EJECT */ -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_DX_DIG */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -127,55 +127,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), -/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10), -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* TS_SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TS_SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -187,12 +187,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* DIG */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* DIG */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_GPI_APIC(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_GPI_APIC(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -204,7 +204,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -216,7 +216,7 @@ static const struct pad_config gpio_table[] = { * SD write protect is not connected but is still sampled, so enable * native function and enable internal pull-down to disable. */ -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -224,16 +224,16 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index e1c2d585fe..7d000f5d6e 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -53,65 +53,65 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ @@ -123,55 +123,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), - PAD_CFG_NC(GPP_D9), - PAD_CFG_NC(GPP_D10), - PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI_IO2 */ PAD_CFG_NC(GPP_D21), -/* TS_SPI_IO3 */ PAD_CFG_NC(GPP_D22), +/* TS_SPI_IO2 */ PAD_NC(GPP_D21, NONE), +/* TS_SPI_IO3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), /* AUDIO_DB_ID */ /* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* TOUCH_RESET */ -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NC(GPP_E22), - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -181,14 +181,14 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -208,24 +208,24 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, 20K_PU, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, 20K_PU, DEEP, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, 20K_PU, DEEP, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, 20K_PU, DEEP, NF1), - PAD_CFG_NC(GPD7), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, UP_20K, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, UP_20K, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, UP_20K, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, UP_20K, DEEP, NF1), + PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NF(GPD10, 20K_PU, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index 06c6e4a8f7..6d415ca30a 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -47,51 +47,51 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), /* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* SM1ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B23, NONE, DEEP), /* UNUSED */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ @@ -100,11 +100,11 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* UNUSED */ /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* UNUSED */ /* SML0ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C5, NONE, DEEP), /* UNUSED */ -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UNUSED */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -117,55 +117,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP), /* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */ -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), /* External pullup */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* External pullup. */ +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -175,13 +175,13 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), @@ -194,15 +194,15 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* RSVD */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -210,18 +210,18 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP), /* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 5361744407..9ee00d2cf9 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -44,10 +44,10 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA# */ /* GPP_A7 */ @@ -70,7 +70,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ /* GPP_B0 */ /* CORE_VID1 */ /* GPP_B1 */ /* VRALERT# */ /* GPP_B2 */ -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, DEEP), /* TRACKPAD */ /* CPU_GP3 */ /* GPP_B4 */ /* SRCCLKREQ0# */ /* GPP_B5 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ @@ -83,7 +83,7 @@ static const struct pad_config gpio_table[] = { /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ /* GPP_B14 */ /* GSPI0_CS# */ /* GPP_B15 */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ /* GSPI0_MISO */ /* GPP_B17 */ /* GSPI0_MOSI */ /* GPP_B18 */ /* GSPI1_CS# */ /* GPP_B19 */ @@ -97,7 +97,7 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UART0_RXD */ /* GPP_C8 */ @@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GPP_D0 */ /* GPP_D1 */ @@ -145,14 +145,14 @@ static const struct pad_config gpio_table[] = { /* GPP_D21 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ /* GPP_E1 */ /* SATAXPCIE2 */ /* GPP_E2 */ /* CPU_GP0 */ /* GPP_E3 */ /* SATA_DEVSLP0 */ /* GPP_E4 */ /* SATA_DEVSLP1 */ /* GPP_E5 */ /* SATA_DEVSLP2 */ /* GPP_E6 */ -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ /* SATALED# */ /* GPP_E8 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -160,8 +160,8 @@ static const struct pad_config gpio_table[] = { /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ /* GPP_E18 */ /* DDPB_CTRLDATA */ /* GPP_E19 */ @@ -184,7 +184,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP), /* MIC_INT_L */ /* I2C5_SCL */ /* GPP_F11 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index d1785cea3c..3d00c353d7 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -43,124 +43,124 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* KEPLR_CLK_REQ */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SSD_CLK_REQ */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* KEPLR_CLK_REQ */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_CLK_REQ */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), /* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), @@ -168,12 +168,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -186,14 +186,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -201,18 +201,18 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 60d93d4308..717e930d24 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -51,137 +51,137 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, DN_20K, DEEP), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -201,7 +201,7 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -209,17 +209,17 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 3a15023894..d3ea6b537b 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -10,73 +10,73 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP726) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> ISH_GP0 */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A21 : ISH_GP3 */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> TRACKPAD_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_A23, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_A23, NONE, DEEP, EDGE_SINGLE, INVERT), /* B0 : CORE_VID0 ==> NC(TP42) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ @@ -86,40 +86,40 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_C10), + PAD_NC(GPP_C10, NONE), /* C11 : UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_C11), + PAD_NC(GPP_C11, NONE), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -133,9 +133,9 @@ static const struct pad_config gpio_table[] = { /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* C18 : I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_C18), + PAD_NC(GPP_C18, NONE), /* C19 : I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_C19), + PAD_NC(GPP_C19, NONE), /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ @@ -143,24 +143,24 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> ISH_I2C0_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), /* D6 : ISH_I2C0_SCL ==> ISH_I2C0_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> SPKR_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D7, NONE, PLTRST), /* D8 : ISH_I2C1_SCL ==> EN_CAMERA_PWR */ PAD_CFG_GPO(GPP_D8, 0, DEEP), /* D9 : ISH_SPI_CS# ==> ISH_SPI_CS_L */ @@ -172,9 +172,9 @@ static const struct pad_config gpio_table[] = { /* D12 : ISH_SPI_MOSI ==> ISH_SPI_MOSI */ PAD_CFG_NF_1V8(GPP_D12, NONE, DEEP, NF1), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : DMIC_CLK1 ==> PCH_CAMERA_RESET */ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* D18 : DMIC_DATA1 ==> PCH_CAMERA_CLOCK_ENABLE */ @@ -184,30 +184,30 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> NC */ - PAD_CFG_NC(GPP_D22), + PAD_NC(GPP_D22, NONE), /* D23 : I2S_MCLK ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> DISPLAY_DCR_EN */ PAD_CFG_GPO(GPP_E6, 1, DEEP), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -215,29 +215,29 @@ static const struct pad_config gpio_table[] = { /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ PAD_CFG_GPO(GPP_E11, 0, DEEP), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ PAD_CFG_GPO(GPP_E15, 1, DEEP), /* E16 : DDPE_HPD3 ==> NC */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> TRACKPAD_SHDN_L */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* F0 : I2S2_SCLK ==> BOOT_BEEP_BCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -246,7 +246,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> BOOT_BEEP_LRCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_TRACKPAD_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_TRACKPAD_1V8_SCL */ @@ -260,7 +260,7 @@ static const struct pad_config gpio_table[] = { /* F9 : I2C4_SCL ==> PCH_I2C4_AUDIO_1V8_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, 20K_PU, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, UP_20K, PLTRST), /* F11 : I2C5_SCL ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* F12 : EMMC_CMD */ @@ -286,7 +286,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -312,23 +312,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -352,10 +352,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -392,14 +392,14 @@ static const struct pad_config ish_disabled_gpio_table[] = { /* A19 : GPP_A19 ==> TRACKPAD_INT_L * trackpad interrupt to PCH */ - PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A19, NONE, PLTRST), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), }; const struct pad_config *variant_sku_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 072b7618a0..dd97d1c6c4 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP41) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP29) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP45) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP67) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,30 +37,30 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A20, NONE, PLTRST), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> WWAN_PCIE_CLKREQ_L */ @@ -68,54 +68,54 @@ static const struct pad_config gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> FP_INT */ - PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_C8, NONE, PLTRST), /* C9 : UART0_TXD ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ @@ -145,12 +145,12 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> EN_PP3300_DX_LTE */ PAD_CFG_GPO(GPP_D0, 1, DEEP), /* D1 : SPI1_CLK ==> PEN_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP), /* D3 : SPI1_MOSI ==> PEN_RST_L */ @@ -162,23 +162,23 @@ static const struct pad_config gpio_table[] = { /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> PEN_EJECT_ODL -- for notification */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_D8, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_D8, UP_20K, DEEP), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> PEN_EJECT_ODL -- for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_D12, 20K_PU, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> LTE_OFF_ODL */ PAD_CFG_GPO(GPP_D16, 1, DEEP), /* D17 : DMIC_CLK1 */ @@ -197,23 +197,23 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -223,27 +223,27 @@ static const struct pad_config gpio_table[] = { /* E12 : USB2_OC3# ==> USB2_OC3_L */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD# */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP244) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP26) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP25) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -352,10 +352,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config * __weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 62d1780c28..6dba783920 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -9,59 +9,59 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP22) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP24) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP15) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP23) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP46) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN#_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> EMMC_RST#L_R_SOC (unstuffed) */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> PCH_SPK_EN */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* B0 : CORE_VID0 ==> NC(T3) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(T4) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> CLKREQ_PCIE#2 */ @@ -71,15 +71,15 @@ static const struct pad_config gpio_table[] = { /* B9 : SRCCLKREQ4# ==> WLAN_PE_RST_AP */ PAD_CFG_GPO(GPP_B9, 0, RSMRST), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> PM_SLP_R_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST#_PCH */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> EC_GPP_B14 (rsvd for later) */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -89,34 +89,34 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC(TP26) */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC(TP27) */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC(TP28) */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC(TP30) */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> SOC_SML1ALERT# (unstuffed) */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> SOC_SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> SOC_SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC(TP917) */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> SOC_SML0ALERT# (unstuffed) */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> TRACKPAD_DISABLE# */ PAD_CFG_GPO(GPP_C7, 1, DEEP), /* C8 : UART0_RXD ==> NC(TP31) */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC(TP32) */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> EN_PP3300_DX_CAM1 */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM2 */ @@ -142,44 +142,44 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> NC(TP926) */ - PAD_CFG_NC(GPP_C22), + PAD_NC(GPP_C22, NONE), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> DDR_CHB_EN (for debugging) */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> PEN_IRQ# */ - PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D1, NONE, PLTRST), /* D2 : SPI1_MISO ==> PEN_PDCT# */ - PAD_CFG_GPI_APIC(GPP_D2, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D2, NONE, PLTRST), /* D3 : SPI1_MOSI ==> PEN_RST# */ PAD_CFG_GPO(GPP_D3, 0, DEEP), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP), /* D11 : ISH_SPI_MISO ==> DCI_CLK (debug header) */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> DCI_DATA (debug header) */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> H1_BOOT_UART_RX (unstuffed) */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> H1_BOOT_UART_TX (unstuffed) */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D18 : DMIC_DATA1 ==> SOC_DMIC_DATA1_R */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* D19 : DMIC_CLK0 ==> SOC_DMIC_CLK0_R */ @@ -187,28 +187,28 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 ==> SOC_DMIC_DATA0_R */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> DDR_CHA_EN (debugging) */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_1_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> EMR_GARAGE_DET# - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, INVERT), /* E2 : SATAXPCIE2 ==> WLAN_OFF# */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> TRACKPAD_INT# */ - PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E3, NONE, PLTRST), /* E4 : SATA_DEVSLP0 ==> BT_OFF# */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* E5 : SATA_DEVSLP1 ==> NC(TP928) */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC(TP915) */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> EMR_GARAGE_DET# - for notification */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E8, NONE, DEEP), /* E9 : USB2_OCO# ==> USB_C0_OC# */ @@ -218,15 +218,15 @@ static const struct pad_config gpio_table[] = { /* E11 : USB2_OC2# ==> USB_A0_OC# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> DDR_SEL */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* E16 : DDPE_HPD3 ==> TRACKPAD_INT# */ - PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* E17 : EDP_HPD ==> EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> SOC_DP1_CTRL_CLK */ @@ -238,9 +238,9 @@ static const struct pad_config gpio_table[] = { /* E21 : DDPC_CTRLDATA ==> SOC_DP2_CTRL_DATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* E22 : DDPD_CTRLCLK ==> WLAN_PCIE_WAKE# */ - PAD_CFG_GPI_ACPI_SCI(GPP_E22, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E22, NONE, DEEP, EDGE_SINGLE, INVERT), /* E23 : DDPD_CTRLDATA ==> NC(TP17)*/ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_2_BCLK_R */ @@ -250,7 +250,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_2_TX_DAC */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> I2C_2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ @@ -260,13 +260,13 @@ static const struct pad_config gpio_table[] = { /* F7 : I2C3_SCL ==> I2C_3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */ - PAD_CFG_NC(GPP_F8), + PAD_NC(GPP_F8, NONE), /* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */ - PAD_CFG_NC(GPP_F9), + PAD_NC(GPP_F9, NONE), /* F10 : I2C5_SDA ==> NC */ - PAD_CFG_NC(GPP_F10), + PAD_NC(GPP_F10, NONE), /* F11 : I2C5_SCL ==> NC */ - PAD_CFG_NC(GPP_F11), + PAD_NC(GPP_F11, NONE), /* F12 : EMMC_CMD ==> EMMC_1_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 ==> EMMC_1_D0 */ @@ -290,24 +290,24 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK ==> EMMC_1_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD ==> NC */ - PAD_CFG_NC(GPP_G0), + PAD_NC(GPP_G0, NONE), /* G1 : SD_DATA0 ==> NC */ - PAD_CFG_NC(GPP_G1), + PAD_NC(GPP_G1, NONE), /* G2 : SD_DATA1 ==> NC */ - PAD_CFG_NC(GPP_G2), + PAD_NC(GPP_G2, NONE), /* G3 : SD_DATA2 ==> NC */ - PAD_CFG_NC(GPP_G3), + PAD_NC(GPP_G3, NONE), /* G4 : SD_DATA3 ==> NC */ - PAD_CFG_NC(GPP_G4), + PAD_NC(GPP_G4, NONE), /* G5 : SD_CD# ==> NC */ - PAD_CFG_NC(GPP_G5), + PAD_NC(GPP_G5, NONE), /* G6 : SD_CLK ==> NC */ - PAD_CFG_NC(GPP_G6), + PAD_NC(GPP_G6, NONE), /* G7 : SD_WP ==> SD_WP (not needed) */ - PAD_CFG_NC(GPP_G7), + PAD_NC(GPP_G7, NONE), /* GPD0: BATLOW# ==> PCH_BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -316,23 +316,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_R_BTN# */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP44) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP41) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP38) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -353,13 +353,13 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SINGLE_CHANNEL */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, 20K_PD, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, DN_20K, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -383,23 +383,23 @@ static const struct pad_config nami_default_sku_gpio_table[] = { static const struct pad_config no_dmic1_sku_gpio_table[] = { /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), }; static const struct pad_config pantheon_gpio_table[] = { /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), }; static const struct pad_config fpmcu_gpio_table[] = { /* B0 : CORE_VID0 ==> FPMCU_INT_L */ - PAD_CFG_GPI_APIC(GPP_B0, NONE, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_B0, NONE, DEEP), /* B1 : CORE_VID1 ==> FPMCU_INT_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B1, 20K_PU, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B1, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_B11, 1, DEEP), /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ @@ -417,7 +417,7 @@ static const struct pad_config fpmcu_gpio_table[] = { /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), /* D17 : DMIC_CLK1 ==> NC */ - PAD_CFG_NC(GPP_D17), + PAD_NC(GPP_D17, NONE), }; const struct pad_config *variant_sku_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 555b532b2c..37378f93a7 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -9,25 +9,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP726) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -38,81 +38,81 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> CPU1_SDCARD_PWREN_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> CHP1_DIG_PDCT_L */ - PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A21, NONE, PLTRST), /* A22 : ISH_GP4 ==> CHP1_DIG_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A22, NONE, PLTRST), /* A23 : ISH_GP5 ==> CHP1_SPK_PA_EN */ PAD_CFG_GPO(GPP_A23, 1, DEEP), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC(TP722) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> CHP3_TP_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> CHP3_TP_INT_L - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* B6 : SRCCLKREQ1# ==> CHP3_WLAN_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> CHP3_WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, DEEP), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> CHP3_SLPS0_L_ORG */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT3_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> CHP3_PEN_EJECT - for notification */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* B20 : GSPI1_CLK ==> LTE3_STRAP# - for SAR sensor presence */ - PAD_CFG_GPI(GPP_B20, 20K_PD, DEEP), + PAD_CFG_GPI(GPP_B20, DN_20K, DEEP), /* B21 : GSPI1_MISO ==> CHP3_PEN_EJECT - for wake event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE), + PAD_CFG_GPI_SCI(GPP_B21, NONE, DEEP, EDGE_SINGLE, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> CHP3_SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> CHP3_SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> CPU3_EC_IN_RW */ - PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */ PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ @@ -144,38 +144,38 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> CHP3_PCH_WP*/ - PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> CHP1_VDD_CAM_CORE_EN */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> CHP1_I2C_ISH_SENSOR_SDA */ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1), /* D6 : ISH_I2C0_SCL ==> CHP1_I2C_ISH_SENSOR_SCL */ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> CHP1_HEADSET_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, UP_20K, DEEP), /* D10 : ISH_SPI_CLK ==> NC */ - PAD_CFG_NC(GPP_D10), + PAD_NC(GPP_D10, NONE), /* D11 : ISH_SPI_MISO ==> NC */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D17 : DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 */ @@ -190,51 +190,51 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> CHP3_HAVEN_INT_L */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> CHP3_TSP_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB3_C1_OC1_L */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB3_C0_OC0_L */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> KBC3_USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> KBC3_USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> CPU3_SD_CD_L */ - PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP766) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> CHP1_CABC */ PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> CHP1_I2S2_SCLK_SPKR_R */ @@ -244,15 +244,15 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> CHP1_I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */ - PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F6, UP_5K, DEEP, NF1), /* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */ - PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1), + PAD_CFG_NF_1V8(GPP_F7, UP_5K, DEEP, NF1), /* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */ @@ -284,7 +284,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -301,7 +301,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> CHP3_BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -310,23 +310,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> KBC3_PCH_WAKE_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> KBC3_PWRBTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> CHP3_SLPS3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> CHP3_SLPS4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP725) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> CHP3_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP724) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP742) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -343,10 +343,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -363,20 +363,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num) static const struct pad_config nautilus_default_sku_gpio_table[] = { /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* E11 : USB2_OC2# ==> USB2_P2_FAULT# */ - PAD_CFG_NF(GPP_E11, 5K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_E11, UP_5K, DEEP, NF1), }; static const struct pad_config lte_sku_gpio_table[] = { /* A18 : ISH_GP0 ==> LTE1_P_SENSOR_INT_L */ - PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_A18, NONE, DEEP), /* D0 : SPI1_CS# ==> LTE_PWROFF# */ PAD_CFG_GPO(GPP_D0, 1, DEEP), /* D16 : ISH_UART0_CTS# ==> LTE3_W_DISABLE# */ diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index d5888dd6f2..f5344584ba 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -8,60 +8,60 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP763) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0_R */ /* A2 : ESPI_IO1_R */ /* A3 : ESPI_IO2_R */ /* A4 : ESPI_IO3_R */ /* A5 : ESPI_CS_L_R */ /* A6 : SERIRQ ==> NC(TP764) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP703) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP758)) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK_R */ - PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF3), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF3), /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PCH_FP_PWR_EN */ PAD_CFG_GPO(GPP_A11, 1, DEEP), /* A12 : ISH_GP6 */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : SD_1P8_SEL ==> NC */ - PAD_CFG_NC(GPP_A16), + PAD_NC(GPP_A16, NONE), /* A17 : SD_PWR_EN# ==> NC */ - PAD_CFG_NC(GPP_A17), + PAD_NC(GPP_A17, NONE), /* A18 : ISH_GP0 ==> ISH_GP0 */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : SPKR_RST_L */ PAD_CFG_GPO(GPP_A19, 1, PLTRST), /* A20 : ISH_GP2 ==> ISH_UART0_RXD */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* B1 : CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> FCAM_PWR_EN */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B6, NONE, DEEP), /* B7 : SRCCLKREQ2# ==> PCIE_NVME_CLKREQ_ODL */ @@ -69,17 +69,17 @@ static const struct pad_config gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> H1_SLAVE_SPI_CLK */ @@ -87,7 +87,7 @@ static const struct pad_config gpio_table[] = { /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ - PAD_CFG_NF(GPP_B18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* B19 : GSPI1_CS# ==> PCH_FPMCU_SPI_CS_L_R */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : GSPI1_CLK ==> PCH_FPMCU_SPI_CLK_R */ @@ -97,32 +97,32 @@ static const struct pad_config gpio_table[] = { /* B22 : GSPI1_MOSI ==> PCH_FPMCU_SPI_MOSI_R */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* B23 : SM1ALERT# ==> PCHHOT# */ - PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), + PAD_CFG_NF(GPP_B23, DN_20K, DEEP, NF2), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# */ - PAD_CFG_NF(GPP_C5, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_C5, DN_20K, DEEP, NF1), /* C6 : SM1CLK ==> EC_IN_RW_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> FPMCU_INT */ - PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, EDGE_SINGLE, INVERT), /* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> FPMCU_INT */ - PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_C11, UP_20K, PLTRST), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -146,34 +146,34 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> RCAM_PWR_EN */ PAD_CFG_GPO(GPP_D7, 0, DEEP), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D10, NONE, PLTRST), /* D11 : ISH_SPI_MISO ==> NC */ - PAD_CFG_NC(GPP_D11), + PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> PCH_FCAM_CLK_EN */ PAD_CFG_GPO(GPP_D13, 0, DEEP), /* D14 : ISH_UART0_TXD ==> PCH_RCAM_CLK_EN */ @@ -183,46 +183,46 @@ static const struct pad_config gpio_table[] = { /* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */ - PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D17, NONE, PLTRST), /* D18 : DMIC_DATA1 ==> TP131 */ - PAD_CFG_NC(GPP_D18), + PAD_NC(GPP_D18, NONE), /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> NC */ - PAD_CFG_NC(GPP_D22), + PAD_NC(GPP_D22, NONE), /* D23 : I2S_MCLK ==> NC */ - PAD_CFG_NC(GPP_D23), + PAD_NC(GPP_D23, NONE), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> WLAN_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_E1, NONE, DEEP, EDGE_SINGLE, INVERT), /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ - PAD_CFG_NC(GPP_E3), + PAD_NC(GPP_E3, NONE), /* E3 : DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ - PAD_CFG_TERM_GPO(GPP_E11, 0, 20K_PD, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 0, DN_20K, DEEP), /* E12 : USB2_OC3# ==> NC */ - PAD_CFG_NC(GPP_E12), + PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C0_DP_HPD */ @@ -230,21 +230,21 @@ static const struct pad_config gpio_table[] = { /* E15 : DDPD_HPD2 ==> EN_PP3300_DX_WLAN */ PAD_CFG_GPO(GPP_E15, 1, DEEP), /* E16 : DDPE_HPD3 ==> NC */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD ==> EDP_HPD_3V3 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> DDPB_CTRLDATA */ - PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> DDPC_CTRLDATA */ - PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* F0 : I2S2_SCLK ==> BOOT_BEEP_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), @@ -253,11 +253,11 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> BOOT_BEEP_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> NC */ - PAD_CFG_NC(GPP_F4), + PAD_NC(GPP_F4, NONE), /* F5 : I2C2_SCL ==> NC */ - PAD_CFG_NC(GPP_F5), + PAD_NC(GPP_F5, NONE), /* F6 : I2C3_SDA ==> PCH_I2C3_FCAM_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> PCH_I2C3_FCAM_1V8_SCL */ @@ -293,24 +293,24 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NC(GPP_G0), + PAD_NC(GPP_G0, NONE), /* G1 : SD_DATA0 */ - PAD_CFG_NC(GPP_G1), + PAD_NC(GPP_G1, NONE), /* G2 : SD_DATA1 */ - PAD_CFG_NC(GPP_G2), + PAD_NC(GPP_G2, NONE), /* G3 : SD_DATA2 */ - PAD_CFG_NC(GPP_G3), + PAD_NC(GPP_G3, NONE), /* G4 : SD_DATA3 */ - PAD_CFG_NC(GPP_G4), + PAD_NC(GPP_G4, NONE), /* G5 : SD_CD# */ - PAD_CFG_NC(GPP_G5), + PAD_NC(GPP_G5, NONE), /* G6 : SD_CLK */ - PAD_CFG_NC(GPP_G6), + PAD_NC(GPP_G6, NONE), /* G7 : SD_WP */ - PAD_CFG_NC(GPP_G7), + PAD_NC(GPP_G7, NONE), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -350,7 +350,7 @@ static const struct pad_config early_gpio_table[] = { /* B17 : GSPI0_MISO ==> H1_SLAVE_SPI_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : GSPI0_MOSI ==> H1_SLAVE_SPI_MOSI */ - PAD_CFG_NF(GPP_B18, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ @@ -359,10 +359,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index 9bb497ec95..8e9e5c01c5 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(T0804) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(T0805) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(T0501) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(T0806) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(T0913) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,48 +37,48 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> NC */ - PAD_CFG_NC(GPP_A20), + PAD_NC(GPP_A20, NONE), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ - PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B0, NONE, DEEP, EDGE_SINGLE, INVERT), /* B1 : CORE_VID1 ==> NC */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> TRACKPAD_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> TRACKPAD_INT_L for wakeup event */ - PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT), + PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, DEEP), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L_PCH */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -88,38 +88,38 @@ static const struct pad_config gpio_table[] = { /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* B19 : GSPI1_CS# ==> NC(T0807) */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC(T0808) */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC(T0809) */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC(T0810) */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA ==> SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> BT_OFF# */ PAD_CFG_GPO(GPP_C8, 1, DEEP), /* C9 : UART0_TXD ==> NC(WLAN_OFF#) */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> NC(T0817) */ - PAD_CFG_NC(GPP_C10), + PAD_NC(GPP_C10, NONE), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ @@ -145,105 +145,105 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC(T0818) */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC(T0819) */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC(T0820) */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC(T0815) */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ - PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), + PAD_CFG_GPI_APIC_HIGH(GPP_D9, UP_20K, DEEP), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> NC(T0816) */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : ISH_UART0_CTS# ==> DMIC_CLK1_PCH */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 ==> NC(T0703) */ - PAD_CFG_NC(GPP_D18), + PAD_NC(GPP_D18, NONE), /* D19 : DMIC_CLK0 ==> DMIC_CLK0_PCH */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : DMIC_DATA0 ==> DMIC_DATA0_PCH */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN I2C OPERATION ENABLE/DISABLE. */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> NC(T0504) */ - PAD_CFG_NC(GPP_E11), + PAD_NC(GPP_E11, NONE), /* E12 : USB2_OC3# ==> USB_A0_OC# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD_ODL */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(T0602) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD ==> EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC*/ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 4 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> I2C_2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK ==> EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD ==> SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK ==> SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP ==> NC(T0701) */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(T0912) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(T0911) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(T0905) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -356,10 +356,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 33bdb290e1..9d52773271 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -8,25 +8,25 @@ /* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { /* A0 : RCIN# ==> NC(TP41) */ - PAD_CFG_NC(GPP_A0), + PAD_NC(GPP_A0, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ - PAD_CFG_NC(GPP_A6), + PAD_NC(GPP_A6, NONE), /* A7 : PIRQA# ==> NC(TP29) */ - PAD_CFG_NC(GPP_A7), + PAD_NC(GPP_A7, NONE), /* A8 : CLKRUN# ==> NC(TP45) */ - PAD_CFG_NC(GPP_A8), + PAD_NC(GPP_A8, NONE), /* A9 : ESPI_CLK */ /* A10 : CLKOUT_LPC1 ==> NC */ - PAD_CFG_NC(GPP_A10), + PAD_NC(GPP_A10, NONE), /* A11 : PME# ==> NC(TP67) */ - PAD_CFG_NC(GPP_A11), + PAD_NC(GPP_A11, NONE), /* A12 : BM_BUSY# ==> NC */ - PAD_CFG_NC(GPP_A12), + PAD_NC(GPP_A12, NONE), /* A13 : SUSWARN# ==> SUSWARN_L */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ @@ -37,87 +37,87 @@ static const struct pad_config gpio_table[] = { /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* A18 : ISH_GP0 ==> NC */ - PAD_CFG_NC(GPP_A18), + PAD_NC(GPP_A18, NONE), /* A19 : ISH_GP1 ==> NC */ - PAD_CFG_NC(GPP_A19), + PAD_NC(GPP_A19, NONE), /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_A20, NONE, PLTRST), /* A21 : ISH_GP3 ==> NC */ - PAD_CFG_NC(GPP_A21), + PAD_NC(GPP_A21, NONE), /* A22 : ISH_GP4 ==> NC */ - PAD_CFG_NC(GPP_A22), + PAD_NC(GPP_A22, NONE), /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + PAD_NC(GPP_A23, NONE), /* B0 : CORE_VID0 ==> NC(TP42) */ - PAD_CFG_NC(GPP_B0), + PAD_NC(GPP_B0, NONE), /* B1 : CORE_VID1 ==> NC(TP43) */ - PAD_CFG_NC(GPP_B1), + PAD_NC(GPP_B1, NONE), /* B2 : VRALERT# ==> NC */ - PAD_CFG_NC(GPP_B2), + PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> NC */ - PAD_CFG_NC(GPP_B3), + PAD_NC(GPP_B3, NONE), /* B4 : CPU_GP3 ==> NC */ - PAD_CFG_NC(GPP_B4), + PAD_NC(GPP_B4, NONE), /* B5 : SRCCLKREQ0# ==> NC */ - PAD_CFG_NC(GPP_B5), + PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* B7 : SRCCLKREQ2# ==> NC */ - PAD_CFG_NC(GPP_B7), + PAD_NC(GPP_B7, NONE), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), /* B9 : SRCCLKREQ4# ==> NC */ - PAD_CFG_NC(GPP_B9), + PAD_NC(GPP_B9, NONE), /* B10 : SRCCLKREQ5# ==> NC */ - PAD_CFG_NC(GPP_B10), + PAD_NC(GPP_B10, NONE), /* B11 : EXT_PWR_GATE# ==> NC */ - PAD_CFG_NC(GPP_B11), + PAD_NC(GPP_B11, NONE), /* B12 : SLP_S0# ==> SLP_S0_L_G */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> NC */ - PAD_CFG_NC(GPP_B14), + PAD_NC(GPP_B14, NONE), /* B15 : GSPI0_CS# ==> NC */ - PAD_CFG_NC(GPP_B15), + PAD_NC(GPP_B15, NONE), /* B16 : GSPI0_CLK ==> NC */ - PAD_CFG_NC(GPP_B16), + PAD_NC(GPP_B16, NONE), /* B17 : GSPI0_MISO ==> NC */ - PAD_CFG_NC(GPP_B17), + PAD_NC(GPP_B17, NONE), /* B18 : GSPI0_MOSI ==> NC */ - PAD_CFG_NC(GPP_B18), + PAD_NC(GPP_B18, NONE), /* B19 : GSPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_B19), + PAD_NC(GPP_B19, NONE), /* B20 : GSPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_B20), + PAD_NC(GPP_B20, NONE), /* B21 : GSPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_B21), + PAD_NC(GPP_B21, NONE), /* B22 : GSPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_B22), + PAD_NC(GPP_B22, NONE), /* B23 : SM1ALERT# ==> NC */ - PAD_CFG_NC(GPP_B23), + PAD_NC(GPP_B23, NONE), /* C0 : SMBCLK ==> NC */ - PAD_CFG_NC(GPP_C0), + PAD_NC(GPP_C0, NONE), /* C1 : SMBDATA ==> NC */ - PAD_CFG_NC(GPP_C1), + PAD_NC(GPP_C1, NONE), /* C2 : SMBALERT# ==> NC */ - PAD_CFG_NC(GPP_C2), + PAD_NC(GPP_C2, NONE), /* C3 : SML0CLK ==> NC */ - PAD_CFG_NC(GPP_C3), + PAD_NC(GPP_C3, NONE), /* C4 : SML0DATA ==> NC */ - PAD_CFG_NC(GPP_C4), + PAD_NC(GPP_C4, NONE), /* C5 : SML0ALERT# ==> NC */ - PAD_CFG_NC(GPP_C5), + PAD_NC(GPP_C5, NONE), /* C6 : SM1CLK ==> EC_IN_RW_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* C7 : SM1DATA ==> NC */ - PAD_CFG_NC(GPP_C7), + PAD_NC(GPP_C7, NONE), /* C8 : UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_C8), + PAD_NC(GPP_C8, NONE), /* C9 : UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_C9), + PAD_NC(GPP_C9, NONE), /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ @@ -145,42 +145,42 @@ static const struct pad_config gpio_table[] = { /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* D0 : SPI1_CS# ==> NC */ - PAD_CFG_NC(GPP_D0), + PAD_NC(GPP_D0, NONE), /* D1 : SPI1_CLK ==> NC */ - PAD_CFG_NC(GPP_D1), + PAD_NC(GPP_D1, NONE), /* D2 : SPI1_MISO ==> NC */ - PAD_CFG_NC(GPP_D2), + PAD_NC(GPP_D2, NONE), /* D3 : SPI1_MOSI ==> NC */ - PAD_CFG_NC(GPP_D3), + PAD_NC(GPP_D3, NONE), /* D4 : FASHTRIG ==> NC */ - PAD_CFG_NC(GPP_D4), + PAD_NC(GPP_D4, NONE), /* D5 : ISH_I2C0_SDA ==> NC */ - PAD_CFG_NC(GPP_D5), + PAD_NC(GPP_D5, NONE), /* D6 : ISH_I2C0_SCL ==> NC */ - PAD_CFG_NC(GPP_D6), + PAD_NC(GPP_D6, NONE), /* D7 : ISH_I2C1_SDA ==> NC */ - PAD_CFG_NC(GPP_D7), + PAD_NC(GPP_D7, NONE), /* D8 : ISH_I2C1_SCL ==> NC */ - PAD_CFG_NC(GPP_D8), + PAD_NC(GPP_D8, NONE), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ - PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_D11, NONE, PLTRST), /* D12 : ISH_SPI_MOSI ==> NC */ - PAD_CFG_NC(GPP_D12), + PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> NC */ - PAD_CFG_NC(GPP_D13), + PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ - PAD_CFG_NC(GPP_D14), + PAD_NC(GPP_D14, NONE), /* D15 : ISH_UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_D15), + PAD_NC(GPP_D15, NONE), /* D16 : ISH_UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_D16), + PAD_NC(GPP_D16, NONE), /* D17 : DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* D18 : DMIC_DATA1 */ @@ -190,30 +190,30 @@ static const struct pad_config gpio_table[] = { /* D20 : DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : SPI1_IO2 ==> NC */ - PAD_CFG_NC(GPP_D21), + PAD_NC(GPP_D21, NONE), /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* D23 : I2S_MCLK ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), /* E1 : SATAXPCIE1 ==> NC */ - PAD_CFG_NC(GPP_E1), + PAD_NC(GPP_E1, NONE), /* E2 : SATAXPCIE2 ==> NC */ - PAD_CFG_NC(GPP_E2), + PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ - PAD_CFG_NC(GPP_E4), + PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ - PAD_CFG_NC(GPP_E5), + PAD_NC(GPP_E5, NONE), /* E6 : SATA_DEVSLP2 ==> NC */ - PAD_CFG_NC(GPP_E6), + PAD_NC(GPP_E6, NONE), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ - PAD_CFG_NC(GPP_E8), + PAD_NC(GPP_E8, NONE), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ @@ -223,27 +223,27 @@ static const struct pad_config gpio_table[] = { /* E12 : USB2_OC3# ==> USB2_OC3_L */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E13, DN_20K, DEEP, NF1), /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_E14, DN_20K, DEEP, NF1), /* E15 : DDPD_HPD2 ==> SD_CD# */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, UP_20K, DEEP), /* E16 : DDPE_HPD3 ==> NC(TP244) */ - PAD_CFG_NC(GPP_E16), + PAD_NC(GPP_E16, NONE), /* E17 : EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* E18 : DDPB_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E18), + PAD_NC(GPP_E18, NONE), /* E19 : DDPB_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E19), + PAD_NC(GPP_E19, NONE), /* E20 : DDPC_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E20), + PAD_NC(GPP_E20, NONE), /* E21 : DDPC_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E21), + PAD_NC(GPP_E21, NONE), /* E22 : DDPD_CTRLCLK ==> NC */ - PAD_CFG_NC(GPP_E22), + PAD_NC(GPP_E22, NONE), /* E23 : DDPD_CTRLDATA ==> NC */ - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E23, NONE), /* The next 3 pads are for bit banging the amplifiers, default to I2S */ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */ @@ -253,7 +253,7 @@ static const struct pad_config gpio_table[] = { /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* F3 : I2S2_RXD ==> NC */ - PAD_CFG_NC(GPP_F3), + PAD_NC(GPP_F3, NONE), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ @@ -293,7 +293,7 @@ static const struct pad_config gpio_table[] = { /* F22 : EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* F23 : RSVD ==> NC */ - PAD_CFG_NC(GPP_F23), + PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), @@ -310,7 +310,7 @@ static const struct pad_config gpio_table[] = { /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* G7 : SD_WP */ - PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* GPD0: BATLOW# ==> PCH_BATLOW_L */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), @@ -319,23 +319,23 @@ static const struct pad_config gpio_table[] = { /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */ - PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4: SLP_S3# ==> SLP_S3_L */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5: SLP_S4# ==> SLP_S4_L */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6: SLP_A# ==> NC(TP26) */ - PAD_CFG_NC(GPD6), + PAD_NC(GPD6, NONE), /* GPD7: RSVD ==> NC */ - PAD_CFG_NC(GPD7), + PAD_NC(GPD7, NONE), /* GPD8: SUSCLK ==> PCH_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9: SLP_WLAN# ==> NC(TP25) */ - PAD_CFG_NC(GPD9), + PAD_NC(GPD9, NONE), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), + PAD_NC(GPD10, NONE), /* GPD11: LANPHYC ==> NC */ - PAD_CFG_NC(GPD11), + PAD_NC(GPD11, NONE), }; /* Early pad configuration in bootblock */ @@ -354,10 +354,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C23 : UART2_CTS# ==> PCH_WP */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */ - PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_E0, NONE, PLTRST), }; const struct pad_config *variant_gpio_table(size_t *num) |