diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-25 08:40:15 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-29 20:47:56 +0000 |
| commit | ffe90c528b0487ce47a123ae905be8823c5615ae (patch) | |
| tree | 9d011606a5318d5d1da7a014cbc92dcf85ecc6ea /src/mainboard/google | |
| parent | 57c8143350bf357dd7edc13ddf735084eea53d07 (diff) | |
| download | coreboot-ffe90c528b0487ce47a123ae905be8823c5615ae.tar.xz | |
soc/intel/skylake: Enable SMBus depending on devicetree configuration
Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/google')
11 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 1af83259be..dfdcf5a4f3 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -32,7 +32,6 @@ chip soc/intel/tigerlake register "SataEnable" = "1" register "SataMode" = "0" register "SataSalpSupport" = "1" - register "SmbusEnable" = "1" # TODO: the lengths are all MID for right now. register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 767c77b907..14d8cc40c3 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -44,7 +44,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 250b96d8ff..0ce9002d7d 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -75,7 +75,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "0" register "ScsEmmcHs400Enabled" = "0" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index bbfa79f1b5..856d749009 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -46,7 +46,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 7c4928d47e..4af8c42958 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -50,7 +50,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" register "ScsEmmcEnabled" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 7bbddbdf3a..bed537bdb6 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" register "ScsEmmcEnabled" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index e9514e0bca..e9f8b1d8a5 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "SaImguEnable" = "0" register "ScsEmmcEnabled" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index e9d7dea3c2..de14503a88 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" register "ScsEmmcEnabled" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index a5c905eed9..24ee14c3d1 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -45,7 +45,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" register "ScsEmmcEnabled" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 32429f9ced..3b9c76168f 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -50,7 +50,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "SaImguEnable" = "0" register "ScsEmmcEnabled" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 2970a2e430..eb3cff351c 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -40,7 +40,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "1" register "SaImguEnable" = "1" register "ScsEmmcEnabled" = "1" |