diff options
| author | Kane Chen <kane_chen@pegatron.corp-partner.google.com> | 2020-08-21 16:55:37 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-08-24 16:53:57 +0000 |
| commit | 0a859522edf75bab86d9c94409485663cbe25cf2 (patch) | |
| tree | e0f36cbbb1e67e9c9cef21d4927eb67e97d99972 /src/mainboard/google | |
| parent | cc69f7b4e59b74990b6023fe6e13d7bcedf0e32e (diff) | |
| download | coreboot-0a859522edf75bab86d9c94409485663cbe25cf2.tar.xz | |
mb/google/zork: Fix GPIO table for v3.6 schematics for woomax
Add board version switch GPIO table on gpio.c.
BUG=b:165887084
BRANCH=Zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I661e16f7b4769e83450f41ff267c0d253441c4cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/zork/variants/woomax/gpio.c | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/src/mainboard/google/zork/variants/woomax/gpio.c b/src/mainboard/google/zork/variants/woomax/gpio.c index 968c622458..ebbcbea624 100644 --- a/src/mainboard/google/zork/variants/woomax/gpio.c +++ b/src/mainboard/google/zork/variants/woomax/gpio.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> -static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { +static const struct soc_amd_gpio woomax_bid0_gpio_set_stage_ram[] = { /* GPIO_4 NC */ PAD_NC(GPIO_4), /* GPIO_5 NC */ @@ -30,8 +30,43 @@ static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { PAD_NC(GPIO_143), }; +static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = { + /* GPIO_4 NC */ + PAD_NC(GPIO_4), + /* GPIO_5 NC */ + PAD_NC(GPIO_5), + /* GPIO_6 NC */ + PAD_NC(GPIO_6), + /* GPIO_11 NC */ + PAD_NC(GPIO_11), + /* GPIO_32 NC */ + PAD_NC(GPIO_32), + /* GPIO_69 NC */ + PAD_NC(GPIO_69), + /* RAM_ID_4 */ + PAD_NC(GPIO_84), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), + /* GPIO_141 NC */ + PAD_NC(GPIO_141), + /* GPIO_143 NC */ + PAD_NC(GPIO_143), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { + uint32_t board_version; + + /* If board version cannot be read, assume it is board_version 0. */ + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 0; + + if (board_version == 0) { + *size = ARRAY_SIZE(woomax_bid0_gpio_set_stage_ram); + return woomax_bid0_gpio_set_stage_ram; + } *size = ARRAY_SIZE(woomax_gpio_set_stage_ram); return woomax_gpio_set_stage_ram; } |