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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2018-12-26 17:26:47 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-01-01 13:30:16 +0000
commit126c27da064ec5e8d141a9b637ba8ed9c59a5b29 (patch)
treef1e1f79ba7eaf0e5d16e938ff2a8703c63c1bc3b /src/mainboard/google
parenta9fadb007ddafd7196f9916439674b63d06e7573 (diff)
downloadcoreboot-126c27da064ec5e8d141a9b637ba8ed9c59a5b29.tar.xz
mb/google/hatch: Enable CNVi Wifi for hatch
This patch enables CNVi wifi for hatch 1. Enable CNVi device in device tree 2. Configure GPIO pad config for CNVi BUG=b:120914069 BRANCH=none TEST=check if code compiles correctly and verify GPIO configuration with schematics Change-Id: I0c5542737d3a629b6a40116b4aa8ab6cbdd6a4dc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30436 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb4
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/gpio.c6
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index c36e582a98..a3d0bc6836 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -154,6 +154,10 @@ chip soc/intel/cannonlake
end
end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_PME_B0"
+ device pci 14.3 on end # CNVi wifi
+ end
device pci 14.5 off end # SDCard
device pci 15.0 on
chip drivers/i2c/generic
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 6bb2e76d4a..8d69682668 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -71,6 +71,12 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_E20, DN_20K),
/* DDPD_CTRLCLK => NC */
PAD_NC(GPP_E22, DN_20K),
+ /* GPIO_WWAN_WLAN_COEX3 */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+ /* UART_WWANTX_WLANRX_COEX1 */
+ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
+ /* UART_WWANRX_WLANTX_COEX2 */
+ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
/* PCH_MEM_STRAP0 */
PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
/* PCH_MEM_STRAP1 */