diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-02 17:27:57 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-06 17:57:40 +0000 |
| commit | 251d305e73f76ca3b63654273f3b2bb3de775457 (patch) | |
| tree | 76cf206b9b73033c21569005f12f80f1df7bbcbf /src/mainboard/google | |
| parent | eb5b0d05a71ec04d69699edebb6e71be2bb6ed09 (diff) | |
| download | coreboot-251d305e73f76ca3b63654273f3b2bb3de775457.tar.xz | |
soc/amd/stoneyridge: Move GPIO support to common
The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product. Move the basic support into a common
directory.
Each product's pin availability, MUXes, and other details must remain
specific to the product.
The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available. The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices. This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.
BUG=b:131682806
Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/kahlee/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/mainboard.c | 3 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/romstage.c | 2 |
3 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 038cfe22c2..3be308e2d3 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -29,7 +29,7 @@ void bootblock_mainboard_early_init(void) mainboard_ec_init(); gpios = variant_early_gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index cfd5637633..f218f3f31b 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -27,6 +27,7 @@ #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> +#include <soc/smi.h> #include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> @@ -126,7 +127,7 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); gpios = variant_gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); /* * Some platforms use SCI not generated by a GPIO pin (event above 23). diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 32f8356521..8bc766e112 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -34,7 +34,7 @@ void mainboard_romstage_entry(int s3_resume) const struct soc_amd_gpio *gpios; gpios = variant_romstage_gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); variant_romstage_entry(s3_resume); } |