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authorAaron Durbin <adurbin@chromium.org>2017-04-19 10:12:47 -0500
committerAaron Durbin <adurbin@chromium.org>2017-04-24 22:15:22 +0200
commit3f98aadacd5ba90d8bf36e448b52d44177760631 (patch)
treef350db40b6e0aa7ee25d82b1444139d5958beaae /src/mainboard/google
parent9d9a121fa0cc0a5b303aaf377ce2a8e426ef0d3a (diff)
downloadcoreboot-3f98aadacd5ba90d8bf36e448b52d44177760631.tar.xz
mainboard/google/poppy: use intel common tis_plat_irq_status()
Utilize the intel/common code for tis_plat_irq_status() to remove dependencies and code duplication on for bringing up a board requiring tis_plat_irq_status(). Change-Id: I2aaa1d7d3ce171dc1788438ff9990fce533deb6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19371 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/Kconfig7
-rw-r--r--src/mainboard/google/poppy/chromeos.c7
2 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index 03ce99b8b9..fa0c6b69b4 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -74,4 +74,11 @@ config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_LID_SWITCH
+config DRIVER_TPM_SPI_BUS
+ default 0x1
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 64 # GPE0_DW2_00 (GPP_E0)
+
endif # BOARD_GOOGLE_BASEBOARD_POPPY
diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c
index e74933dd7b..cf9579ed9c 100644
--- a/src/mainboard/google/poppy/chromeos.c
+++ b/src/mainboard/google/poppy/chromeos.c
@@ -17,9 +17,7 @@
#include <baseboard/variants.h>
#include <gpio.h>
#include <rules.h>
-#include <soc/gpe.h>
#include <soc/gpio.h>
-#include <tpm.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
@@ -56,8 +54,3 @@ void mainboard_chromeos_acpi_generate(void)
gpios = variant_cros_gpios(&num);
chromeos_acpi_gpio_generate(gpios, num);
}
-
-int tis_plat_irq_status(void)
-{
- return acpi_get_gpe(GPE0_DW2_00);
-}