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| author | FrankChu <frank_chu@pegatron.corp-partner.google.com> | 2021-03-23 18:24:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-25 07:50:17 +0000 |
| commit | 6902263dca82c9e08d48554cc1daffc8dfd6b6de (patch) | |
| tree | 8e4f88c9a3d22103368a17417b5b19c776458aea /src/mainboard/google | |
| parent | 2bb7896c366258c46e8125aad63ffe09c87ad5ec (diff) | |
| download | coreboot-6902263dca82c9e08d48554cc1daffc8dfd6b6de.tar.xz | |
mb/google/volteer: Collis: Update SPD table
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/collis/memory/ src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt
DRAM Part Name ID to assign
MT53D512M64D4NW-046 WT:F 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
BUG=b:182227204
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I773c65c0b6d5e868572530305ab8a61a0dd1532d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google')
5 files changed, 77 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/collis/Makefile.inc b/src/mainboard/google/volteer/variants/collis/Makefile.inc new file mode 100644 index 0000000000..9064208bff --- /dev/null +++ b/src/mainboard/google/volteer/variants/collis/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/collis/memory.c b/src/mainboard/google/volteer/variants/collis/memory.c new file mode 100644 index 0000000000..b4414d4019 --- /dev/null +++ b/src/mainboard/google/volteer/variants/collis/memory.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + .ddr1 = { + .dq0 = { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + .ddr2 = { + .dq0 = { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + .ddr3 = { + .dq0 = { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + .ddr4 = { + .dq0 = { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + .ddr5 = { + .dq0 = { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + .ddr6 = { + .dq0 = { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + .ddr7 = { + .dq0 = { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = true, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/collis/memory/Makefile.inc b/src/mainboard/google/volteer/variants/collis/memory/Makefile.inc index b0ca2223a8..7b9a85e0d6 100644 --- a/src/mainboard/google/volteer/variants/collis/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/collis/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53D512M64D4NW-046 WT:F, H9HCNNNCRMBLPR-NEE +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53D1G64D4NW-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNFBMBLPR-NEE diff --git a/src/mainboard/google/volteer/variants/collis/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/collis/memory/dram_id.generated.txt index fa247902ee..413301e52c 100644 --- a/src/mainboard/google/volteer/variants/collis/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/collis/memory/dram_id.generated.txt @@ -1 +1,5 @@ DRAM Part Name ID to assign +MT53D512M64D4NW-046 WT:F 0 (0000) +H9HCNNNCRMBLPR-NEE 0 (0000) +MT53D1G64D4NW-046 WT:A 1 (0001) +H9HCNNNFBMBLPR-NEE 2 (0010) diff --git a/src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt new file mode 100644 index 0000000000..c1d262300c --- /dev/null +++ b/src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +MT53D512M64D4NW-046 WT:F +H9HCNNNCRMBLPR-NEE +MT53D1G64D4NW-046 WT:A +H9HCNNNFBMBLPR-NEE |