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authorLijian Zhao <lijian.zhao@intel.com>2018-12-26 19:53:32 -0800
committerDuncan Laurie <dlaurie@chromium.org>2019-01-04 01:15:00 +0000
commit768cd37bc3aa399488bf299486b46e1b1d4f1da7 (patch)
tree676b413f95d75f581b93efd0be5f1793f466f861 /src/mainboard/google
parentdff185a28d00700660c14535e4d7e53f7fbc3eec (diff)
downloadcoreboot-768cd37bc3aa399488bf299486b46e1b1d4f1da7.tar.xz
mb/google/sarien: Add settings for noise mitgation
Enable acoustic noise mitgation for sarien platform, the slow slew rates are fast time dived by 8. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28 Reviewed-on: https://review.coreboot.org/c/30448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 47abadc5d9..0b8e5c6519 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -33,6 +33,11 @@ chip soc/intel/cannonlake
register "dptf_enable" = "1"
register "dmipwroptimize" = "1"
register "satapwroptimize" = "1"
+ register "AcousticNoiseMitigation" = "1"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
+ register "SlowSlewRateForSa" = "2"
+ register "SlowSlewRateForFivr" = "2"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port