mainboard/*/romstage.c: Sanitize system header inclusions

Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.

Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

6 files changed, 26 insertions, 26 deletions

diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 6cf86ada5a..70a6f444c7 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -31,10 +31,10 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index f58ab1359c..873de91321 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -32,10 +32,10 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
 #include "ec/google/chromeec/ec.h"
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 69711d9203..7d67abd181 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -31,10 +31,10 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c
index 38c224b2c0..9a1fb769a8 100644
--- a/src/mainboard/google/peppy/romstage.c
+++ b/src/mainboard/google/peppy/romstage.c
@@ -24,12 +24,12 @@
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include "cpu/intel/haswell/haswell.h"
+#include <cpu/intel/haswell/haswell.h>
 #include "ec/google/chromeec/ec.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "gpio.h"
 #include "onboard.h"
 
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index fd190ed714..6feebac28c 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -24,11 +24,11 @@
 #include <string.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include "cpu/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/lp_gpio.h"
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "gpio.h"
 
 const struct rcba_config_instruction rcba_config[] = {
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index e8f2927526..f856c59d2f 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -31,10 +31,10 @@
 #include <arch/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>