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authorLijian Zhao <lijian.zhao@intel.com>2018-11-14 16:15:46 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-11-17 07:25:54 +0000
commit79152f3c811879cc61576b7d8788d7bdda17066d (patch)
tree1c41115b6bfdb3702c2da016d9f1e19760121763 /src/mainboard/google
parent28114ae71bd94c5db17073e1e9a96173331055be (diff)
downloadcoreboot-79152f3c811879cc61576b7d8788d7bdda17066d.tar.xz
soc/intel/cannonlake: Add options for pcie ltr
FSP can support enable/disable Pci express LTR (Latency Tolerance Reporting) mechanism through upd interface. Include that into coreboot side. BUG=N/A TEST=N/A Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29642 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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