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authorGabe Black <gabeblack@google.com>2014-02-15 00:05:03 -0800
committerMarc Jones <marc.jones@se-eng.com>2014-11-13 06:23:46 +0100
commit83ed805cd992a0b3d3e4e9df8f13b7b9e8f38866 (patch)
tree3210e858d260f680801f0f06893dbee7a59c36b0 /src/mainboard/google
parent558e9b55c8394d760603247fe7407a40206f5220 (diff)
downloadcoreboot-83ed805cd992a0b3d3e4e9df8f13b7b9e8f38866.tar.xz
nyan: big: Check dram_end when setting up caching in ROM stage.
When setting up caching on nyan and big, we would set the region after DRAM to the end of the address space as uncachable. DRAM may actually extend beyond the end of the address space, so that may result in address aliasing or other problems. This change adds a check to make sure there's actually space there. BUG=None TEST=Built for big. BRANCH=None Original-Change-Id: Ic0a98550222f9dfc0aeafd67a2dd1c0c8f4ece44 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186769 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1866a4d2a001beb97779b611b8b69c63175048f4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If1ca8b5bd4efab8962e03c0d9eaa70c0327ea6b5 Reviewed-on: http://review.coreboot.org/7405 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/nyan/romstage.c3
-rw-r--r--src/mainboard/google/nyan_big/romstage.c3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 7fb9570669..28827c8d5f 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -93,7 +93,8 @@ static void __attribute__((noinline)) romstage(void)
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ if (dram_end < 4096)
+ mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index c18138ae90..0fbe316882 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -93,7 +93,8 @@ static void __attribute__((noinline)) romstage(void)
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
- mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+ if (dram_end < 4096)
+ mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();