diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-09-05 14:23:27 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-06 16:40:01 +0000 |
| commit | 8688536ca201c7dfa77b570036c5759ff998df91 (patch) | |
| tree | 6613082907d812672445e36476f5e97c1c1cadf4 /src/mainboard/google | |
| parent | 6ab4ed40d355a55f0ff8e8aade55be796a256c0d (diff) | |
| download | coreboot-8688536ca201c7dfa77b570036c5759ff998df91.tar.xz | |
mb/google/soraka: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0.
Change-Id: I76742801e84449d0910ddadf31d39597df3263b9
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 3ac3aaf953..87e4b836e7 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -152,6 +152,8 @@ chip soc/intel/skylake register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" + # RP 1, Enable Advanced Error Reporting + register PcieRpAdvancedErrorReporting[0] = "1" register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port |