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authorShaunak Saha <shaunak.saha@intel.com>2020-09-22 23:09:24 -0700
committerNick Vaccaro <nvaccaro@google.com>2020-10-14 16:46:17 +0000
commitb27b0fd2ac06e9aa8bafb8f780e5859da5bf6420 (patch)
tree652205b2b19033c448c922e219f85f15b17c9985 /src/mainboard/google
parent7ded1afe0a518c65c5f2850984419287ac880fa1 (diff)
downloadcoreboot-b27b0fd2ac06e9aa8bafb8f780e5859da5bf6420.tar.xz
mb/google/volteer: Disable HybridStorageMode for volteer baseboard
HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer baseboard. For boards using optane HybridStorage needs to be enabled from overwrite devicetree. We are enabling HybridStorage for volteer and volteer2 as those plaforms have SKU's with optane storage. BUG=b:158573805 TEST=Build and boot non optane device and confirm that FspSiliconInit time is reduced. This saves ~100ms. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb2
-rw-r--r--src/mainboard/google/volteer/variants/volteer/overridetree.cb2
-rw-r--r--src/mainboard/google/volteer/variants/volteer2/overridetree.cb2
3 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 330accca40..28d903f7a3 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -87,7 +87,7 @@ chip soc/intel/tigerlake
# Enable Optane PCIE 11 using clk 0
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
- register "HybridStorageMode" = "1"
+ register "HybridStorageMode" = "0"
# Enable SD Card PCIE 8 using clk 3
register "PcieRpEnable[7]" = "1"
diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
index 5079493437..2c120d59c7 100644
--- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb
@@ -47,6 +47,8 @@ chip soc/intel/tigerlake
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
+ register "HybridStorageMode" = "1"
+
device domain 0 on
device ref ipu on end
device ref i2c0 on
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index f8dcd58cc2..d49a52a89b 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -5,6 +5,8 @@ chip soc/intel/tigerlake
register "DdiPort1Hpd" = "0"
register "DdiPort2Hpd" = "0"
+ register "HybridStorageMode" = "1"
+
device domain 0 on
device ref dptf on
chip drivers/intel/dptf