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authorRob Barnes <robbarnes@google.com>2020-09-25 14:16:46 -0600
committerFurquan Shaikh <furquan@google.com>2020-10-14 04:47:39 +0000
commitd1095c7ed79d7bed958c6e446fe4ea2def5c2102 (patch)
treef6353842fd314eba14621e31d9aa67514cd3a635 /src/mainboard/google
parent0aed4e577df03a3c9c790fddebb1a9c413a0abcb (diff)
downloadcoreboot-d1095c7ed79d7bed958c6e446fe4ea2def5c2102.tar.xz
mb/google/zork: Enable wake on wireless lan
Add generic wifi ACPI entry for wake on lan event. Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI. BUG=b:162605108 TEST=$ iw phy phy0 wowlan enable disconnect $ cat /proc/acpi/wakeup | grep WF WF00 S3 *enabled pci:0000:01:00.0 $ powerd_dbus_suspend Reboot wifi router, DUT wakes up BRANCH=zork Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb7
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb7
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c4
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c4
4 files changed, 16 insertions, 6 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index cbb812d220..58e25e6ba3 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -210,7 +210,12 @@ chip soc/amd/picasso
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge, must be enabled
device pci 1.1 off end # GPP Bridge 0
- device pci 1.2 on end # GPP Bridge 1 - Wifi
+ device pci 1.2 on # GPP Bridge 1 - Wifi
+ chip drivers/wifi/generic
+ register "wake" = "GEVENT_8"
+ device pci 00.0 on end
+ end
+ end
device pci 1.3 on end # GPP Bridge 2 - SD
device pci 1.4 off end # GPP Bridge 3
device pci 1.5 off end # GPP Bridge 4
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 7288d6e32d..3ab70a2945 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -210,7 +210,12 @@ chip soc/amd/picasso
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge, must be enabled
device pci 1.1 off end # GPP Bridge 0
- device pci 1.2 on end # GPP Bridge 1 - Wifi
+ device pci 1.2 on # GPP Bridge 1 - Wifi
+ chip drivers/wifi/generic
+ register "wake" = "GEVENT_8"
+ device pci 00.0 on end
+ end
+ end
device pci 1.3 on end # GPP Bridge 2 - SD
device pci 1.4 off end # GPP Bridge 3
device pci 1.5 off end # GPP Bridge 4
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index 696c733189..2398d07d74 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -14,8 +14,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
/* SYS_RESET_L */
PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
- /* PCIE_WAKE_L */
- PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
+ /* WIFI_PCIE_WAKE_ODL */
+ PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW),
/* H1_FCH_INT_ODL */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* PEN_DETECT_ODL */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 549cc589bb..a436d1c3d0 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -14,8 +14,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
/* SYS_RESET_L */
PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
- /* PCIE_WAKE_L */
- PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
+ /* WIFI_PCIE_WAKE_ODL */
+ PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW),
/* H1_FCH_INT_ODL */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* PEN_DETECT_ODL */