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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-02-04 08:31:18 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-04 16:15:04 +0000 |
| commit | e65f500a0b90ccbf1a172427b7a61a047571ff02 (patch) | |
| tree | 1fc026841a81b5822a05826e11bff6ca514923b8 /src/mainboard/google | |
| parent | 4d9d3f164de7002dd38f12dc40f9b260f63d2d9b (diff) | |
| download | coreboot-e65f500a0b90ccbf1a172427b7a61a047571ff02.tar.xz | |
mb/google/hatch: Enable Audio DSP oscillator qualification for S0ix
BUG=b:139481313
Change-Id: I1a0911b7967e5823fdce98195420728bd38c80f6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index e0291bbd3f..f7cf3cd466 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -142,6 +142,9 @@ chip soc/intel/cannonlake register "PchPmSlpSusMinAssert" = "1" # 500ms register "PchPmSlpAMinAssert" = "3" # 2s + # Enable Audio DSP oscillator qualification for S0ix + register "cppmvric2_adsposcdis" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 |