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| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-09-30 08:26:00 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-30 12:01:08 +0000 |
| commit | ff5eb86aeb3e2129882120150132ba83dd1efea0 (patch) | |
| tree | e416267a46eb946df0eda5a31fa92fda98a7c404 /src/mainboard/google | |
| parent | 0e1245e3d065287b3f731e92fa45811225462532 (diff) | |
| download | coreboot-ff5eb86aeb3e2129882120150132ba83dd1efea0.tar.xz | |
mb/google/drallion: Clean up devicetree config
* Disable SATA controller and related configs.
* Disable PCIe root ports 10 and related configs.
-> Board uses integrated CnVi for WLAN
* Disable PCIe root ports 12 and related configs.
-> Board uses WWAN intarfaced over USB
Change-Id: If9d49cef290dcccb114afccc3ac34cd072802ea4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35723
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/devicetree.cb | 21 |
1 files changed, 3 insertions, 18 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 2e8edd5b0e..db3f36bc8d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -31,10 +31,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "0" - register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -47,7 +43,6 @@ chip soc/intel/cannonlake register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" register "Device4Enable" = "1" @@ -202,16 +197,6 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" - # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[1]" = "9" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe port 12 for M.2 3042 WWAN - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[0]" = "11" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" @@ -395,7 +380,7 @@ chip soc/intel/cannonlake device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 off end # SATA device pci 19.0 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -417,9 +402,9 @@ chip soc/intel/cannonlake device pci 1d.0 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) |