diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-03-26 04:25:46 +0100 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2013-03-26 04:39:53 +0100 |
| commit | 0175587c5ea1db0ef76b3000db027e353b383de9 (patch) | |
| tree | a31ebe07ca31bcb28cc8dff3384d30c9239678a7 /src/mainboard/google | |
| parent | 7f86c0586add7836b8c44805b6ef9eaa59fac787 (diff) | |
| download | coreboot-0175587c5ea1db0ef76b3000db027e353b383de9.tar.xz | |
Revert "samsung/exynos5: add resource functions for the display port"
This reverts commit 9427ca151e44644238b1b52138894195a9f5175f
Looks like we were a bit too anxious to see this one get in. The devicetree.cb change seems to have broken things.
coreboot memory table:
0. 0000000050000000-000000005000ffff: RESERVED
1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES
2. 0000014004000000-00000140044007ff: RESERVED
Before this patch:
coreboot memory table:
0. 0000000040000000-00000000bfefffff: RAM
1. 00000000bff00000-00000000bfffffff: CONFIGURATION TABLES
Change-Id: I618e4f1976265d56cfd6a61d0c5736c55a0f3cec
Reviewed-on: http://review.coreboot.org/2914
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/snow/devicetree.cb | 38 |
1 files changed, 25 insertions, 13 deletions
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index cfe5cf183d..5ad786ef55 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -17,18 +17,30 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# FIXME: this is just a stub for now chip cpu/samsung/exynos5250 - device cpu_cluster 0 on end - register "xres" = "1366" - register "yres" = "768" - register "bpp" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" - register "lcdbase" = "0x50000000" + +device cpu_cluster 0 on +end + +device domain 0 on + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end + chip cpu/samsung/exynos5-common/displayport + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" + end +end end |