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authorKane Chen <kane.chen@intel.com>2019-09-25 11:41:15 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-10-22 20:10:28 +0000
commit0bc35af93326ec3232ec73c9b1334241b85f0252 (patch)
tree13173cb7094e0c2045513d238b7278ba2a2d3284 /src/mainboard/google
parent58e96705cbc78d3f1f330945b1f16b3fae277427 (diff)
downloadcoreboot-0bc35af93326ec3232ec73c9b1334241b85f0252.tar.xz
mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch
On hatch and variant HW designs supports VCCPRIM_CORE Low Voltage Mode. VCCPRIM_CORE can be down to 0.75v when slp_s0 is asserted. This commit enables PchPmSlpS0Vm075VSupport UPD so that FSP can program related setttings to save power. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: Ia02ff8823883489b36349457213409496f082f36 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 7382209264..a2831e1bba 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -58,6 +58,8 @@ chip soc/intel/cannonlake
register "PmTimerDisabled" = "1"
+ register "PchPmSlpS0Vm075VSupport" = "1"
+
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |