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authorRaul E Rangel <rrangel@chromium.org>2019-06-12 16:38:15 -0600
committerMartin Roth <martinroth@google.com>2019-06-19 19:29:35 +0000
commit1264d64a742e6f911b77dd8c63eeebdba94389a6 (patch)
treec52901dbe4914ca2799c2652ef6422973703fb89 /src/mainboard/google
parentce2b2bad77716821235335cda9ede3849fb28e09 (diff)
downloadcoreboot-1264d64a742e6f911b77dd8c63eeebdba94389a6.tar.xz
grunt: Change Bayhub eMMC base clock to 200MHz
The clock was previously set to 52MHz to workaround the fact that depthcharge didn't support tuning. Tuning has now been enabled in depthcharge: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553 BUG=b:122244718 TEST=Verified on grunt that it speeds up boot by 130ms Change-Id: If847cea2a7848bcd175958db86e652d4f710201a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/mainboard.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
index 996e6102fc..95274eb85d 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
@@ -61,12 +61,22 @@ void board_bh720(struct device *dev)
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
- /* Set Bayhub SD base CLK 50MHz: case#1 PCR 0x3E4[22] = 0 */
+ /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL);
+ bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
+ bh720_pcr_data &= 0x0000FFFF;
+ bh720_pcr_data |= 0x2510 << 16;
+ write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data);
+ write32((void *)(sdbar + BH720_MEM_RW_ADR),
+ BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL);
+
+ /* Use PLL Base clock PCR 0x3E4[22] = 1 */
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_READ | BH720_PCR_CSR);
bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
write32((void *)(sdbar + BH720_MEM_RW_DATA),
- bh720_pcr_data & ~BH720_PCR_CSR_EMMC_MODE_SEL);
+ bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL);
write32((void *)(sdbar + BH720_MEM_RW_ADR),
BH720_MEM_RW_WRITE | BH720_PCR_CSR);