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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-04-21 17:59:25 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-04-25 19:28:47 +0000
commit184b1ce1714cbdd934494280dfcbf473972c12df (patch)
tree95755f64181957d4cb235606fef949073759a1f6 /src/mainboard/google
parentfadd6353dbe72bec79888b37385df7f5877ddc1a (diff)
downloadcoreboot-184b1ce1714cbdd934494280dfcbf473972c12df.tar.xz
mb/google/deltaur: Move early gpio table to variants
If set variant early gpio table NULL, it will override the baseboard table. Move early gpio table to variant level. BUG=b:154310066 TEST=Check H1 has no I2C error occurs. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie4c4648ccf918446a499019a4f77f64e43a92c76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/gpio.c42
-rw-r--r--src/mainboard/google/deltaur/variants/deltan/gpio.c35
2 files changed, 36 insertions, 41 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c
index 71a07b6d46..a96e702fac 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/gpio.c
+++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c
@@ -406,44 +406,6 @@ const struct pad_config *__weak variant_base_gpio_table(size_t *num)
return gpio_table;
}
-/* GPIO pads configured in bootblock */
-static const struct pad_config early_gpio_table[] = {
- /* A23 : GPP_A23 ==> RECOVERY# */
- PAD_CFG_GPI(GPP_A23, NONE, DEEP),
- /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */
- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
- /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */
- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
- /* C22 : GPP_C22 ==> H1_FLASH_WP */
- PAD_CFG_GPI(GPP_C22, NONE, DEEP),
- /* C23 : GPP_C23 ==> H1_PCH_INT# */
- PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT),
- /* E3 : GPP_E3 ==> MEM_INTERLEAVED */
- PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
- /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */
- PAD_CFG_GPI(GPP_F11, NONE, DEEP),
- /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */
- PAD_CFG_GPI(GPP_F12, NONE, DEEP),
- /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */
- PAD_CFG_GPI(GPP_F13, NONE, DEEP),
- /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */
- PAD_CFG_GPI(GPP_F14, NONE, DEEP),
- /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */
- PAD_CFG_GPI(GPP_F15, NONE, DEEP),
- /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */
- PAD_CFG_GPO(GPP_F16, 0, DEEP),
- /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */
- PAD_CFG_GPI(GPP_H4, NONE, DEEP),
- /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */
- PAD_CFG_GPI(GPP_H5, NONE, DEEP),
- /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */
- PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
- /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */
- PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
- /* GPD3: GPD3 ==> SIO_PWRBTN# */
- PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
-};
-
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_NAME),
@@ -465,8 +427,8 @@ const struct pad_config *__weak variant_override_gpio_table(size_t *num)
/* Weak implementation of early gpio */
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
{
- *num = ARRAY_SIZE(early_gpio_table);
- return early_gpio_table;
+ *num = 0;
+ return NULL;
}
int __weak has_360_sensor_board(void)
diff --git a/src/mainboard/google/deltaur/variants/deltan/gpio.c b/src/mainboard/google/deltaur/variants/deltan/gpio.c
index 30315bbc2e..f67302f117 100644
--- a/src/mainboard/google/deltaur/variants/deltan/gpio.c
+++ b/src/mainboard/google/deltaur/variants/deltan/gpio.c
@@ -21,7 +21,40 @@ const struct pad_config *variant_override_gpio_table(size_t *num)
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
-
+ /* A23 : GPP_A23 ==> RECOVERY# */
+ PAD_CFG_GPI(GPP_A23, NONE, DEEP),
+ /* C20 : GPP_C20 ==> PCHRX_SERVOTX_UART */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* C21 : CPP_G21 ==> PCHTX_SERVORX_UART */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ /* C22 : GPP_C22 ==> H1_FLASH_WP */
+ PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+ /* C23 : GPP_C23 ==> H1_PCH_INT# */
+ PAD_CFG_GPI_APIC(GPP_C23, NONE, DEEP, LEVEL, INVERT),
+ /* E3 : GPP_E3 ==> MEM_INTERLEAVED */
+ PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
+ /* F11 : GPP_F11 ==> MEM_CONFIG0_1P8 */
+ PAD_CFG_GPI(GPP_F11, NONE, DEEP),
+ /* F12 : GPP_F12 ==> MEM_CONFIG1_1P8 */
+ PAD_CFG_GPI(GPP_F12, NONE, DEEP),
+ /* F13 : GPP_F13 ==> MEM_CONFIG2_1P8 */
+ PAD_CFG_GPI(GPP_F13, NONE, DEEP),
+ /* F14 : GPP_F14 ==> MEM_CONFIG3_1P8 */
+ PAD_CFG_GPI(GPP_F14, NONE, DEEP),
+ /* F15 : GPP_F15 ==> MEM_CONFIG4_1P8 */
+ PAD_CFG_GPI(GPP_F15, NONE, DEEP),
+ /* F16 : GPP_F16 ==> WWAN_BB_RST#_1P8 */
+ PAD_CFG_GPO(GPP_F16, 0, DEEP),
+ /* H4 : GPP_H4 ==> DDR_CHA_EN_1P8 */
+ PAD_CFG_GPI(GPP_H4, NONE, DEEP),
+ /* H5 : GPP_H5 ==> DDR_CHB_EN_1P8 */
+ PAD_CFG_GPI(GPP_H5, NONE, DEEP),
+ /* H6 : GPP_H6 ==> I2C_SDA_PCH_H1 */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : GPP_H7 ==> I2C_SCL_PCH_H1 */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* GPD3: GPD3 ==> SIO_PWRBTN# */
+ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
};
const struct pad_config *variant_early_gpio_table(size_t *num)