bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.

Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6921
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 5 insertions, 80 deletions

diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 03d499d69c..908b6d869e 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -117,8 +117,6 @@ void main(unsigned long bist)
 {
 	int boot_mode = 0;
 	int cbmem_was_initted;
-	u32 pm1_cnt;
-	u16 pm1_sts;
 
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,
@@ -202,24 +200,7 @@ void main(unsigned long bist)
 	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 
-	/* Check PM1_STS[15] to see if we are waking from Sx */
-	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
-	/* Read PM1_CNT[12:10] to determine which Sx state */
-	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
-	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-		if (acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			boot_mode = 2;
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		}
-	}
+	boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
 
 	post_code(0x38);
 	/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index ca58262b91..8236e2062d 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -155,8 +155,6 @@ void main(unsigned long bist)
 {
 	int boot_mode = 0;
 	int cbmem_was_initted;
-	u32 pm1_cnt;
-	u16 pm1_sts;
 
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -239,24 +237,8 @@ void main(unsigned long bist)
 	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 
-	/* Check PM1_STS[15] to see if we are waking from Sx */
-	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
-	/* Read PM1_CNT[12:10] to determine which Sx state */
-	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
-	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-		if (acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			boot_mode = 2;
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		}
-	} else {
+	boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
+	if (boot_mode == 0) {
 		/* This is the fastest way to let users know
 		 * the Intel CPU is now alive.
 		 */
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 667d639d5a..ce42b4126e 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -118,8 +118,6 @@ void main(unsigned long bist)
 {
 	int boot_mode = 0;
 	int cbmem_was_initted;
-	u32 pm1_cnt;
-	u16 pm1_sts;
 
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
@@ -202,24 +200,7 @@ void main(unsigned long bist)
 	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 
-	/* Check PM1_STS[15] to see if we are waking from Sx */
-	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
-	/* Read PM1_CNT[12:10] to determine which Sx state */
-	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
-	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-		if (acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			boot_mode = 2;
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		}
-	}
+	boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
 
 	post_code(0x38);
 	/* Enable SPD ROMs and DDR-III DRAM */
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 7ac5297d5a..bfa4af703e 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -159,8 +159,6 @@ void main(unsigned long bist)
 {
 	int boot_mode = 0;
 	int cbmem_was_initted;
-	u32 pm1_cnt;
-	u16 pm1_sts;
 
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,
@@ -249,24 +247,7 @@ void main(unsigned long bist)
 	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 
-	/* Check PM1_STS[15] to see if we are waking from Sx */
-	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
-	/* Read PM1_CNT[12:10] to determine which Sx state */
-	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
-	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-		if (acpi_s3_resume_allowed()) {
-			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-			boot_mode = 2;
-			/* Clear SLP_TYPE. This will break stage2 but
-			 * we care for that when we get there.
-			 */
-			outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-		} else {
-			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-		}
-	}
+	boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
 
 	/* Do ec reset as early as possible, but skip it on S3 resume */
 	if (boot_mode < 2)