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authorV Sowmya <v.sowmya@intel.com>2017-05-23 14:17:01 +0530
committerDuncan Laurie <dlaurie@chromium.org>2017-05-25 16:14:49 +0200
commit41f937382d3631c4b9e7ff3744fb68535044da8b (patch)
tree088e330ee6783a8e76770f1f9fad3669b2f53741 /src/mainboard/google
parent34dba35831f8c46ea96a9049737b4a367b1b6460 (diff)
downloadcoreboot-41f937382d3631c4b9e7ff3744fb68535044da8b.tar.xz
mainboard/google/eve: Update VR config settings
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:38415991 BRANCH=none TEST=Build and boot eve. Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/19826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/eve/devicetree.cb26
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index a7388b945b..487dda3f35 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -68,7 +68,7 @@ chip soc/intel/skylake
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
- #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi2Threshold | 2A | 2A | 2A | 2A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
@@ -76,13 +76,13 @@ chip soc/intel/skylake
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 4A | 24A | 24A | 24A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
- #| AcLoadline | 17.9 | 5.9 | 5.7 | 5.7 |
- #| DcLoadline | 14 | 4.7 | 4.2 | 4.2 |
+ #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 |
+ #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(4),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
@@ -90,14 +90,14 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(4),
.voltage_limit = 1520,
- .ac_loadline = 1790,
- .dc_loadline = 1400,
+ .ac_loadline = 1490,
+ .dc_loadline = 1420,
}"
register "domain_vr_config[VR_IA_CORE]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
@@ -105,14 +105,14 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
- .ac_loadline = 590,
- .dc_loadline = 470,
+ .ac_loadline = 500,
+ .dc_loadline = 486,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
@@ -127,7 +127,7 @@ chip soc/intel/skylake
register "domain_vr_config[VR_GT_SLICED]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
- .psi2threshold = VR_CFG_AMP(5),
+ .psi2threshold = VR_CFG_AMP(2),
.psi3threshold = VR_CFG_AMP(1),
.psi3enable = 1,
.psi4enable = 1,
@@ -135,8 +135,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
- .ac_loadline = 570,
- .dc_loadline = 420,
+ .ac_loadline = 457,
+ .dc_loadline = 430,
}"
# Enable Root port 1 with SRCCLKREQ1#