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| author | Hung-Te Lin <hungte@chromium.org> | 2013-04-25 16:14:19 +0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-04-25 19:27:48 +0200 |
| commit | 55c753d3a948fc06d8ccbc3cef678ef2e71f616f (patch) | |
| tree | 9b2a44488640ea50a0310cc942f46f35dd62926a /src/mainboard/google | |
| parent | 175ad4aa6eca2d7f884745959bd175b37c5ffc31 (diff) | |
| download | coreboot-55c753d3a948fc06d8ccbc3cef678ef2e71f616f.tar.xz | |
arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.
To support suspend/resume, PHY control must be reset only on normal boot
path. So add a new param "mem_reset" to specify that.
Verified to boot successfully on Google/Snow.
Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3128
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/snow/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 41b88e1e5f..edbe00919f 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -184,7 +184,7 @@ void main(void) mem->mpll_mdiv, mem->frequency_mhz); - ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE); + ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1); if (ret) { printk(BIOS_ERR, "Memory controller init failed, err: %x\n", ret); |