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authorFurquan Shaikh <furquan@chromium.org>2017-04-03 21:52:39 -0700
committerFurquan Shaikh <furquan@google.com>2017-04-05 17:59:26 +0200
commit66386d24974e158e7be0c7fed50da654275474e3 (patch)
tree392c943bd6fb9524074611aaf84d7598daee77cb /src/mainboard/google
parentc5f10f9d857215319c015af3673fadfe1ff3de34 (diff)
downloadcoreboot-66386d24974e158e7be0c7fed50da654275474e3.tar.xz
mainboard/google/poppy: Change SD card detect to GPP_E15
SD card detect pin is moved to GPP_E15 in the next build. Update device tree and gpio config accordingly. BUG=b:36012095 Change-Id: Ic0ff72cdcb0f1ca27abc7eb8da9ccd8a21b28522 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19107 Tested-by: build bot (Jenkins) Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/devicetree.cb2
-rw-r--r--src/mainboard/google/poppy/gpio.h4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
index 7bf28d0b31..fcf106683e 100644
--- a/src/mainboard/google/poppy/devicetree.cb
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -177,7 +177,7 @@ chip soc/intel/skylake
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
- register "sdcard_cd_gpio_default" = "GPP_A7"
+ register "sdcard_cd_gpio_default" = "GPP_E15"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h
index 5fa8244c75..be7a488d5b 100644
--- a/src/mainboard/google/poppy/gpio.h
+++ b/src/mainboard/google/poppy/gpio.h
@@ -48,7 +48,7 @@ static const struct pad_config gpio_table[] = {
/* ESPI_IO3 */
/* ESPI_CS# */
/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP44 */
-/* PIRQA# */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* SD_CD# */
+/* PIRQA# */ PAD_CFG_NC(GPP_A7),
/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP45 */
/* ESPI_CLK */
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
@@ -166,7 +166,7 @@ static const struct pad_config gpio_table[] = {
NF1), /* USB_C0_DP_HPD */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP,
NF1), /* USB_C1_DP_HPD */
-/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP48 */
+/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP), /* SD_CD# */
/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP244 */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),