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authorLijian Zhao <lijian.zhao@intel.com>2018-12-06 17:07:25 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-19 05:30:52 +0000
commit6b2c9b17514d10f61106c50580ea6c0f33345e00 (patch)
tree79550d82c046b2913d7f7ff5d45403a4c7d7d9a6 /src/mainboard/google
parentba8202948ab77bdbd3dc2197f1552b87791a659a (diff)
downloadcoreboot-6b2c9b17514d10f61106c50580ea6c0f33345e00.tar.xz
mb/google/sarien: Use meaningful SATA mode
Define SATA mode to AHCI mode instead of 0, make devicetree more readable. BUG=N/A Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb2
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 18bd155afa..acdb623319 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -17,7 +17,7 @@ chip soc/intel/cannonlake
register "SaGv" = "3"
register "HeciEnabled" = "1"
register "SataSalpSupport" = "1"
- register "SataMode" = "0"
+ register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
register "InternalGfx" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 771bec2cb9..2800ff588c 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -17,7 +17,7 @@ chip soc/intel/cannonlake
register "SaGv" = "3"
register "HeciEnabled" = "1"
register "SataSalpSupport" = "1"
- register "SataMode" = "0"
+ register "SataMode" = "Sata_AHCI"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"