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authorLijian Zhao <lijian.zhao@intel.com>2018-12-21 19:36:35 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-29 07:12:56 +0000
commit78824238b9613b7927f94db252ed174c86709098 (patch)
tree7ac34c944e09d599705cc2354b9514a1a7a30ed0 /src/mainboard/google
parent8ae54188531ddadcb252b7c266c475bf1e462b9b (diff)
downloadcoreboot-78824238b9613b7927f94db252ed174c86709098.tar.xz
mb/google/sarien: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf Reviewed-on: https://review.coreboot.org/c/30374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/sarien/variants/sarien/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 38d21c87ee..3f43e73422 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -213,7 +213,6 @@ static const struct pad_config gpio_table[] = {
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
-/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
@@ -237,6 +236,7 @@ static const struct pad_config early_gpio_table[] = {
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
+/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */
};
const struct pad_config *variant_gpio_table(size_t *num)