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authorThejaswani Putta <thejaswani.putta@intel.corp-partner.google.com>2019-09-20 15:13:22 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-10-02 11:23:45 +0000
commit86cb421df68f8c22b3cc27fb9ef45a6633724bb6 (patch)
tree139d5f8d7662399a193ff38a4cb83f1d90e806d4 /src/mainboard/google
parent459f4934867a74e71868d3ea55f637782fd2f8cd (diff)
downloadcoreboot-86cb421df68f8c22b3cc27fb9ef45a6633724bb6.tar.xz
mb/google/drallion: Disable GBE in firmware for drallion variants
BUG: None TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
index f2367ffa1d..8cb1aa3001 100644
--- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb
@@ -417,6 +417,6 @@ chip soc/intel/cannonlake
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
- device pci 1f.6 on end # GbE
+ device pci 1f.6 off end # GbE
end
end