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authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 16:42:33 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:46:26 +0000
commit9c538348d8ccaef2c3dd6b898a1f44b00ea59690 (patch)
tree79eac3af79546b14b110b059e31eb18d33de4ce0 /src/mainboard/google
parent934b8da442a04978c6320299c616d3e8f05cb731 (diff)
downloadcoreboot-9c538348d8ccaef2c3dd6b898a1f44b00ea59690.tar.xz
nb/intel/sandybridge: Make the mainboard_rcba_config hook optional
This also changes the name to mainboard_late_rcba_config to better reflect what it does. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/butterfly/romstage.c2
-rw-r--r--src/mainboard/google/link/romstage.c2
-rw-r--r--src/mainboard/google/parrot/romstage.c2
-rw-r--r--src/mainboard/google/stout/romstage.c2
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 449ccf507e..3aef9d0a09 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -35,7 +35,7 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
}
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
{
u32 reg32;
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index d42572b632..628e2a0052 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -39,7 +39,7 @@ void pch_enable_lpc(void)
GAMEL_LPC_EN | COMA_LPC_EN);
}
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
{
/*
* GFX INTA -> PIRQA (MSI)
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 8893819446..604cf7b284 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -30,7 +30,7 @@ void pch_enable_lpc(void)
{
}
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
{
u32 reg32;
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 6690c6863c..cbbae2ee07 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -43,7 +43,7 @@ void pch_enable_lpc(void)
CNF1_LPC_EN | FDD_LPC_EN);
}
-void mainboard_rcba_config(void)
+void mainboard_late_rcba_config(void)
{
u32 reg32;