diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-05-23 15:57:46 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:37:57 +0100 |
| commit | b1c25e74af0a7b1cb4aae0fc9ab8147ee9d14907 (patch) | |
| tree | dc46deac7f5c9c16e64ac7c569eaf854a7dd4b8a /src/mainboard/google | |
| parent | 5290f71569d1bf8b6fa80d34f4b176407082fec8 (diff) | |
| download | coreboot-b1c25e74af0a7b1cb4aae0fc9ab8147ee9d14907.tar.xz | |
haswell: update pei_data data structure
Update and use the new pei_data data structure. Now that the
reference code is fixed it's possible to properly disable/enable
the USB2 and USB3 ports correctly.
Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4185
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/falco/romstage.c | 26 | ||||
| -rw-r--r-- | src/mainboard/google/slippy/romstage.c | 26 |
2 files changed, 34 insertions, 18 deletions
diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 7dde91ff58..3bf1dbd300 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -124,15 +124,23 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, max_ddr3_freq: 1600, - usb_port_config: { - { 1, 0, 0x0040 }, /* P0: USB3 Port A */ - { 1, 0, 0x0040 }, /* P1: USB3 Port B */ - { 1, 0, 0x0040 }, /* P2: CCD */ - { 1, 0, 0x0040 }, /* P3: BT */ - { 1, 0, 0x0040 }, /* P4: LTE */ - { 1, 0, 0x0040 }, /* P5: TOUCH */ - { 1, 0, 0x0040 }, /* P6: SD Card */ - { 1, 0, 0x0040 }, /* P7: USB2 Port */ + usb2_ports: { + /* Length, Enable, OCn# */ + { 0x0040, 1, 0 }, /* P0: Port A, CN8 */ + { 0x0040, 1, 0 }, /* P1: Port B, CN9 */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ + { 0x0040, 1, 3 }, /* P7: USB2 Port */ + }, + usb3_ports: { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN8 */ + { 1, 0 }, /* P2; Port B, CN9 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ }, }; diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 01f613d45c..8679adb202 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -158,15 +158,23 @@ void mainboard_romstage_entry(unsigned long bist) dimm_channel0_disabled: 2, dimm_channel1_disabled: 2, max_ddr3_freq: 1600, - usb_port_config: { - { 1, 0, 0x0040 }, /* P0: LTE */ - { 1, 0, 0x0040 }, /* P1: USB3 Port A */ - { 1, 0, 0x0040 }, /* P2: CCD */ - { 1, 0, 0x0040 }, /* P3: BT */ - { 1, 0, 0x0040 }, /* P4: USB3 Port B */ - { 0, 0, 0x0040 }, /* P5: EMPTY */ - { 1, 0, 0x0040 }, /* P6: SD Card */ - { 0, 0, 0x0040 }, /* P7: EMPTY */ + usb2_ports: { + /* Length, Enable, OCn# */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ + { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ + { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ + { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ + { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ + { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ + }, + usb3_ports: { + /* Enable, OCn# */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN6 */ + { 0, USB_OC_PIN_SKIP }, /* P3; */ + { 0, USB_OC_PIN_SKIP }, /* P4; */ }, }; |