rk3288: add ddr driver

Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321
Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209465
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8865
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

6 files changed, 236 insertions, 0 deletions

diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc
index 50a6ba039b..f249cf95af 100644
--- a/src/mainboard/google/veyron/Makefile.inc
+++ b/src/mainboard/google/veyron/Makefile.inc
@@ -18,6 +18,7 @@
 ##
 
 romstage-y += romstage.c
+romstage-y += sdram_configs.c
 ramstage-y += mainboard.c
 ramstage-y += chromeos.c
 
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index 5b26f48e3c..5831fde095 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -27,6 +27,7 @@
 #include <timestamp.h>
 #include <arch/cache.h>
 #include <arch/exception.h>
+#include <soc/rockchip/rk3288/sdram.h>
 
 void main(void)
 {
@@ -36,6 +37,7 @@ void main(void)
 	u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
 	u32 dram_size = CONFIG_DRAM_SIZE_MB;
 	u32 dram_end = dram_start + dram_size;
+	sdram_init(get_sdram_config());
 	mmu_init();
 	/* Device memory below DRAM is uncached. */
 	mmu_config_range(0, dram_start, DCACHE_OFF);
diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c
new file mode 100644
index 0000000000..b3600fbfff
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_configs.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <arch/io.h>
+#include <string.h>
+#include <types.h>
+#include <console/console.h>
+#include <soc/rockchip/rk3288/sdram.h>
+#include <soc/rockchip/rk3288/gpio.h>
+
+static struct rk3288_sdram_params sdram_configs[] = {
+#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0001 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0011 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0100 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0101 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0110 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0111 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1000 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1001 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1010 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1011 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1101 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1110 */
+#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1111 */
+};
+
+#define GPIO_RAMCODE0	(gpio_t){.port = 8, .bank = GPIO_A, .idx = 0}
+#define GPIO_RAMCODE1	(gpio_t){.port = 8, .bank = GPIO_A, .idx = 1}
+#define GPIO_RAMCODE2	(gpio_t){.port = 8, .bank = GPIO_A, .idx = 2}
+#define GPIO_RAMCODE3	(gpio_t){.port = 8, .bank = GPIO_A, .idx = 3}
+
+u32 sdram_get_ram_code(void)
+{
+	u32 code = 0;
+
+	gpio_input(GPIO_RAMCODE0);
+	gpio_input(GPIO_RAMCODE1);
+	gpio_input(GPIO_RAMCODE2);
+	gpio_input(GPIO_RAMCODE3);
+
+	code = gpio_get_in_value(GPIO_RAMCODE3) << 3
+			| gpio_get_in_value(GPIO_RAMCODE2) << 2
+			| gpio_get_in_value(GPIO_RAMCODE1) << 1
+			| gpio_get_in_value(GPIO_RAMCODE0) << 0;
+
+	return code;
+}
+
+const struct rk3288_sdram_params *get_sdram_config()
+{
+	u32 ramcode = sdram_get_ram_code();
+
+	if (ramcode >= ARRAY_SIZE(sdram_configs)
+			|| sdram_configs[ramcode].dramtype == UNUSED)
+		die("Invalid RAMCODE.");
+	return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
new file mode 100644
index 0000000000..409a7cad35
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-ddr3-hynix-2GB.inc
@@ -0,0 +1,77 @@
+{
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x1,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x1F4,
+		.togcnt100n = 0x35,
+		.trefi = 0x4E,
+		.tmrd = 0x4,
+		.trfc = 0xBB,
+		.trp = 0x8,
+		.trtw = 0x4,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x6,
+		.tras = 0x14,
+		.trc = 0x1D,
+		.trcd = 0x8,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x200,
+		.txp = 0x4,
+		.txpdll = 0xD,
+		.tzqcs = 0x40,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x6,
+		.tcksrx = 0x6,
+		.tcke = 0x4,
+		.tmod = 0xC,
+		.trstl = 0x36,
+		.tzqcl = 0x100,
+		.tmrr = 0x0,
+		.tckesr = 0x5,
+		.tdpd = 0x0
+	},
+	{
+		.dtpr0 = 0x3AD48890,
+		.dtpr1 = 0xBB08D8,
+		.dtpr2 = 0x1002B600,
+		.mr[0] = 0x840,
+		.mr[1] = 0x40,
+		.mr[2] = 0x8,
+		.mr[3] = 0x0
+	},
+	.noc_timing = 0x2891E41D,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533000000,
+	.dramtype = DDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
new file mode 100644
index 0000000000..315e542c39
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB.inc
@@ -0,0 +1,78 @@
+{
+	/* two Samsung K4E8E304ED-EGCE000 chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xE,
+			.cs1_row = 0xE
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 2,
+	.ddr_freq = 533000000,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 1
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
new file mode 100644
index 0000000000..06498f7f14
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-unused.inc
@@ -0,0 +1,3 @@
+{
+	.dramtype= UNUSED
+},
\ No newline at end of file