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authorJulius Werner <jwerner@chromium.org>2013-08-06 16:00:37 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 22:46:15 +0100
commitce011ec1317eebdcec91f29d206869ac0a71c23a (patch)
tree9ef9a4996eec6c559a785078c669924e0f2edaf1 /src/mainboard/google
parent20316321fbf4cab423961f73df31795ec6dea670 (diff)
downloadcoreboot-ce011ec1317eebdcec91f29d206869ac0a71c23a.tar.xz
exynos5250: Implement support to boot with USB A-A firmware upload
This patch implements the basic infrastructure required to use the USB A-A firmware upload feature on Exynos5 processors with Coreboot. It will require a corresponding host-side script that activates the feature and uploads the correct image parts in the correct order to harcoded target addresses, as described in the comments of alternate_cbfs.c. Also fixes a bug in the Google Snow mainboard where it would not correctly initialize the pinmux configuration for the SPI flash bus. During a normal SPI boot the IROM would already do that for you, but when booting from USB you have to do it yourself. Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64875 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4456 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/snow/romstage.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 92fa21e4a1..d45b8613c3 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -180,7 +180,8 @@ void main(void)
setup_gpio();
setup_graphics();
- /* Set SPI (primary CBFS media) clock to 50MHz. */
+ /* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */
+ exynos_pinmux_spi1();
clock_set_rate(PERIPH_ID_SPI1, 50000000);
cbmem_initialize_empty();