diff options
author | Martin Roth <martinroth@google.com> | 2017-10-23 12:07:24 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-11-13 20:19:43 +0000 |
commit | fa3aff09067bec65558174c30a93be0fbaa5bc44 (patch) | |
tree | 460d9fa9a929b8caf276eb4c6ad40358bb1eafc7 /src/mainboard/google | |
parent | ac35e622c2974304b538292088f5110c181085f5 (diff) | |
download | coreboot-fa3aff09067bec65558174c30a93be0fbaa5bc44.tar.xz |
mainboard/google/kahlee: Add Grunt variant framework
Update common files and add files for grunt to the variant directory.
BUG=b:68293392
TEST=Build only
Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
5 files changed, 92 insertions, 5 deletions
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index e38fef9be5..7173f1daa3 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -13,10 +13,8 @@ # GNU General Public License for more details. # -if BOARD_GOOGLE_KAHLEE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y +config BOARD_GOOGLE_BASEBOARD_KAHLEE + bool select SOC_AMD_STONEYRIDGE_FT4 select BOARD_ROMSIZE_KB_8192 select DRIVERS_PS2_KEYBOARD @@ -31,16 +29,20 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select STONEYRIDGE_UART +if BOARD_GOOGLE_BASEBOARD_KAHLEE + config MAINBOARD_DIR string default google/kahlee config VARIANT_DIR string + default "grunt" if BOARD_GOOGLE_GRUNT default "kahlee" if BOARD_GOOGLE_KAHLEE config MAINBOARD_PART_NUMBER string + default "Grunt" if BOARD_GOOGLE_GRUNT default "Kahlee" if BOARD_GOOGLE_KAHLEE config DEVICETREE @@ -78,10 +80,11 @@ config CHROMEOS config GBB_HWID string depends on CHROMEOS + default "GRUNT TEST XXXX" if BOARD_GOOGLE_GRUNT default "KAHLEE TEST 6421" if BOARD_GOOGLE_KAHLEE config AMD_FWM_POSITION_INDEX int default 1 -endif # BOARD_GOOGLE_KAHLEE +endif # BOARD_GOOGLE_KAHLEE || BOARD_GOOGLE_GRUNT diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index 8b2174b16e..d03d88ebdb 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -1,2 +1,6 @@ +config BOARD_GOOGLE_GRUNT + bool "Grunt" + select BOARD_GOOGLE_BASEBOARD_KAHLEE config BOARD_GOOGLE_KAHLEE bool "Kahlee" + select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb new file mode 100644 index 0000000000..6558dec013 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -0,0 +1,48 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # + device pci 2.2 on end # + device pci 2.3 on end # + device pci 2.4 on end # + device pci 2.5 on end # + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SMbus + end # SMbus + device pci 14.3 on + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/usb_oc.asl new file mode 100644 index 0000000000..d22628c7c0 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/usb_oc.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/usb_oc.asl> diff --git a/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h new file mode 100644 index 0000000000..5a6b54044f --- /dev/null +++ b/src/mainboard/google/kahlee/variants/grunt/include/variant/gpio.h @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> |