diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-06-21 22:27:19 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-25 08:10:04 +0000 |
| commit | 2ef3b2df1f562610219444d913224d0600c097a1 (patch) | |
| tree | 3ede558a643317670cc346a8e7859137d47fdec8 /src/mainboard/google | |
| parent | 8302585c152926c086107cdf11f48040d0d873d5 (diff) | |
| download | coreboot-2ef3b2df1f562610219444d913224d0600c097a1.tar.xz | |
mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table
This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.
A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
3 files changed, 2 insertions, 12 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index e903700d0f..a4e86487bd 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -13,6 +13,8 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_NF(GPIO_19, I2C3_SCL, PULL_UP), /* I2C3_SDA - H1 */ PAD_NF(GPIO_20, I2C3_SDA, PULL_UP), + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* FCH_ESPI_EC_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* ESPI_ALERT_L (may be unused) */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 35e1829f89..ba50362685 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -15,9 +15,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { /* EC_FCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), - /* PCIE_RST0_L - Fixed timings */ - /* TODO: Make sure this gets locked at end of post */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -52,9 +49,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = { /* EC_FCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), - /* PCIE_RST0_L - Fixed timings */ - /* TODO: Make sure this gets locked at end of post */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 3f02f00e25..01aef2bb11 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -15,9 +15,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { /* EC_FCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), - /* PCIE_RST0_L - Fixed timings */ - /* TODO: Make sure this gets locked at end of post */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -50,9 +47,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = { /* EC_FCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), - /* PCIE_RST0_L - Fixed timings */ - /* TODO: Make sure this gets locked at end of post */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ |