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| author | Tim Chen <tim-chen@quanta.corp-partner.google.com> | 2018-04-12 07:39:40 +0000 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-04-13 16:45:47 +0000 |
| commit | 5d27f40418973ac09b0aa5d6289648f9b77b4952 (patch) | |
| tree | 3a4e57ccf27e780f9ec21864b1b0ef9dbbcb1ce2 /src/mainboard/google | |
| parent | 48e074975d518239b69a4a303cce5ace6b500f13 (diff) | |
| download | coreboot-5d27f40418973ac09b0aa5d6289648f9b77b4952.tar.xz | |
Revert "mb/google/reef: Override USB2 phy settings"
This reverts commit 70ba1b7e78930acca578114cdadcbcec367730e8.
This commit can only pass far-end USB eye diagram but will fail on near-end.
Confirmed with Intel we should revert it.
Change-Id: I6de44d5240393409d9ec5835a9de0c23453300f7
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25630
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/devicetree.cb | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index a8e24cdec9..da47d42d32 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -116,22 +116,6 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" - # Override USB2 PER PORT register (PORT 1) - register "usb2eye[1]" = "{ - .Usb20PerPortPeTxiSet = 4, - .Usb20PerPortTxiSet = 4, - .Usb20IUsbTxEmphasisEn = 1, - .Usb20PerPortTxPeHalf = 0, - }" - - # Override USB2 PER PORT register (PORT 4) - register "usb2eye[4]" = "{ - .Usb20PerPortPeTxiSet = 7, - .Usb20PerPortTxiSet = 7, - .Usb20IUsbTxEmphasisEn = 1, - .Usb20PerPortTxPeHalf = 0, - }" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |