summaryrefslogtreecommitdiff
path: root/src/mainboard/google
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2013-07-09 11:08:52 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-12-12 22:03:54 +0100
commita367892c98a8ae84470a28ab2d9e4dd8a09596b4 (patch)
treec875baf2dcd2a906c65736417e4f8ff261757d3f /src/mainboard/google
parent7ed39767048c535217bb741e1d0f0f365f598f10 (diff)
downloadcoreboot-a367892c98a8ae84470a28ab2d9e4dd8a09596b4.tar.xz
falco: fix usb port settings
USB2 Port A set to 6.4" and Back Panel USB2 Port B set to 5.2" and Back Panel USB2 Port C set to 12.3" and Internal Other devices all set to Internal. build and boot on falco and check settings. Based on the config settings all ports end up with tuning param 1 == 5 and param 2 == 2 U2ECR[0] = 0x00059501 U2ECR[1] = 0x00059501 U2ECR[2] = 0x00059501 U2ECR[3] = 0x00059501 U2ECR[4] = 0x00059501 U2ECR[5] = 0x00059501 U2ECR[6] = 0x00059501 U2ECR[7] = 0x00059e01 Change-Id: I6b9e6df2679036a501355e6b389a486a6f178f99 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61297 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4350 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/falco/romstage.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c
index e284491bbd..fcf06a918b 100644
--- a/src/mainboard/google/falco/romstage.c
+++ b/src/mainboard/google/falco/romstage.c
@@ -134,22 +134,22 @@ void mainboard_romstage_entry(unsigned long bist)
max_ddr3_freq: 1600,
usb2_ports: {
/* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, /* P0: Port A, CN8 */
+ { 0x0064, 1, 0, /* P0: Port A, CN8 */
USB_PORT_BACK_PANEL },
- { 0x0040, 1, 0, /* P1: Port B, CN9 */
+ { 0x0052, 1, 0, /* P1: Port B, CN9 */
USB_PORT_BACK_PANEL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
- USB_PORT_MINI_PCIE },
+ USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
- USB_PORT_MINI_PCIE },
+ USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
- USB_PORT_FLEX },
+ USB_PORT_INTERNAL },
{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
- USB_PORT_FLEX },
- { 0x0040, 1, 3, /* P7: USB2 Port */
- USB_PORT_FRONT_PANEL },
+ USB_PORT_INTERNAL },
+ { 0x0123, 1, 3, /* P7: USB2 Port */
+ USB_PORT_INTERNAL },
},
usb3_ports: {
/* Enable, OCn# */